Stats

  • Locked Locked
  • Replies 6
  • Subscribers 125
  • Views 15503
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Abstract generator gdsii file import problem

Dinesh Varma4

Hello,

First I exported  File-> export-> stream. and .lef file of inverter designed using cms9flp technology

Once the file were exported then i invoked abstract generator and i gave library, when i was trying to import gdsii file i am getting the following errors.

ERROR ABS-216: There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection ofLEFDefaultRouteSpec constraint group of the technology file. These layers must have the layer function metal in the functions section. Update the technology file and attach it again.

ERROR ABS-218

There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file. In addition, ensure that the function argument is set to 'cut' for the via in the functions subsection of the layerRules section and then try again.

I updated the technology file which was suggested by cadence help but still i am getting the same error

can some one please help me to resolve this error.

I really appreciate your time

Thanks.

DInesh

Parents

  • Hi Quek,

    currently i am  IC6.1.5.500.17 Version of abstract generator

    b) May i know what do you mean by modified tech file

    this is how i am generating .tf file CIW tools-> technology file manager -> dump all ,

    i tried to generate .tf file multiple times, each time it is giving me different output file.

    In .tf file i have "virtuosoDefaultExtractorSetup" in my constracint group in that i have only valid layers

    validLayers   (LD  VV  OL  JT  M1_2B  V0_2B  M5  V4  M4  V3  M3  V2  M2  V1  M1  CA  PC  RX  ) )

    I have seen in one of post that if  we have this "virtuosoDefaultExtractorSetup" then we have to paste this in general-> constraint

    After "virtuosoDefaultExtractorSetup"  function i have "LEFDefaultRouteSpec" which has routingGrids

    and validLayers   (M1  M2  M3  M4  M5  M1_2B  OL  LD

    Default values of horizontalPitch, verticalPitch in routingGrids are 0 so i updated the values to respective minimum spacing to all metals

    validvias section is in  "LEFSpecialRouteSpec" instead of LEFDefaultRouteSpec

    validVias    (VPC_M1  VDPC_M1  VRX_M1  VDRX_M1  VM1_M2  VDM1_M2  VM2_M3  VDM2_M3  VM3_M4  VDM3_M4  VM4_M5  VDM4_M5  VM5_M1_2B  VDM5_M1_2B  VM1_2B_OL  VDM1_2B_OL  VOL_LD  VDOL_LD  ) )

Reply

  • Hi Quek,

    currently i am  IC6.1.5.500.17 Version of abstract generator

    b) May i know what do you mean by modified tech file

    this is how i am generating .tf file CIW tools-> technology file manager -> dump all ,

    i tried to generate .tf file multiple times, each time it is giving me different output file.

    In .tf file i have "virtuosoDefaultExtractorSetup" in my constracint group in that i have only valid layers

    validLayers   (LD  VV  OL  JT  M1_2B  V0_2B  M5  V4  M4  V3  M3  V2  M2  V1  M1  CA  PC  RX  ) )

    I have seen in one of post that if  we have this "virtuosoDefaultExtractorSetup" then we have to paste this in general-> constraint

    After "virtuosoDefaultExtractorSetup"  function i have "LEFDefaultRouteSpec" which has routingGrids

    and validLayers   (M1  M2  M3  M4  M5  M1_2B  OL  LD

    Default values of horizontalPitch, verticalPitch in routingGrids are 0 so i updated the values to respective minimum spacing to all metals

    validvias section is in  "LEFSpecialRouteSpec" instead of LEFDefaultRouteSpec

    validVias    (VPC_M1  VDPC_M1  VRX_M1  VDRX_M1  VM1_M2  VDM1_M2  VM2_M3  VDM2_M3  VM3_M4  VDM3_M4  VM4_M5  VDM4_M5  VM5_M1_2B  VDM5_M1_2B  VM1_2B_OL  VDM1_2B_OL  VOL_LD  VDOL_LD  ) )

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.