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Abstract generator gdsii file import problem

Dinesh Varma4

Hello,

First I exported  File-> export-> stream. and .lef file of inverter designed using cms9flp technology

Once the file were exported then i invoked abstract generator and i gave library, when i was trying to import gdsii file i am getting the following errors.

ERROR ABS-216: There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection ofLEFDefaultRouteSpec constraint group of the technology file. These layers must have the layer function metal in the functions section. Update the technology file and attach it again.

ERROR ABS-218

There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file. In addition, ensure that the function argument is set to 'cut' for the via in the functions subsection of the layerRules section and then try again.

I updated the technology file which was suggested by cadence help but still i am getting the same error

can some one please help me to resolve this error.

I really appreciate your time

Thanks.

DInesh

  • Hi Dinesh

    Would you please help to provide the following info?

    a. Version of abstract generator.
    terminal>abstract -W

    b. If you export the modified techfile, do you see modifications?

    c. Would you please post your current validLayers and validVias lines for LEFDefaultRouteSpec constraint group?

    Best regards
    Quek

  • Hi Quek,

    currently i am  IC6.1.5.500.17 Version of abstract generator

    b) May i know what do you mean by modified tech file

    this is how i am generating .tf file CIW tools-> technology file manager -> dump all ,

    i tried to generate .tf file multiple times, each time it is giving me different output file.

    In .tf file i have "virtuosoDefaultExtractorSetup" in my constracint group in that i have only valid layers

    validLayers   (LD  VV  OL  JT  M1_2B  V0_2B  M5  V4  M4  V3  M3  V2  M2  V1  M1  CA  PC  RX  ) )

    I have seen in one of post that if  we have this "virtuosoDefaultExtractorSetup" then we have to paste this in general-> constraint

    After "virtuosoDefaultExtractorSetup"  function i have "LEFDefaultRouteSpec" which has routingGrids

    and validLayers   (M1  M2  M3  M4  M5  M1_2B  OL  LD

    Default values of horizontalPitch, verticalPitch in routingGrids are 0 so i updated the values to respective minimum spacing to all metals

    validvias section is in  "LEFSpecialRouteSpec" instead of LEFDefaultRouteSpec

    validVias    (VPC_M1  VDPC_M1  VRX_M1  VDRX_M1  VM1_M2  VDM1_M2  VM2_M3  VDM2_M3  VM3_M4  VDM3_M4  VM4_M5  VDM4_M5  VM5_M1_2B  VDM5_M1_2B  VM1_2B_OL  VDM1_2B_OL  VOL_LD  VDOL_LD  ) )

  • Even though i added validvias section in "virtuosoDefaultExtractorSetup"

    still i am having the following error

    ABS-270 : valid vias not present in interconnect section in the virtuosoDefaultExtractorSetup constraint group. please add vias section

    ABS-263 : the routing direction for layer M1 is specified but no pitch value is present in the technology file

    ABS-218 There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file. In addition, ensure that the function argument is set to 'cut' for the via in the functions subsection of the layerRules section and then try again.

    could you please tell me where i am going wrong

  • I finally able to resolve this error.

    The problem is when ever i was giving my library  its not using the technology library that i dumped and modified.

    Once i made changes to my .tf file, i created new library with the modified tech file.

  • in reply to Dinesh Varma4
    Dinesh Varma4 said:
    The problem is when ever i was giving my library  its not using the technology library that i dumped and modified.

    Can you tell how exactly you resolved this error?
    I have drawn schematics and layouts and created symbols for basic gates (and2, or2, nand2, nor2, xor2, inv) usign Virtuoso. I want to use these for synthesis with Cadence Genus.
    Is this possible?

    The training videos provided for the COS account only tell me how to use Genus. Can you please guide me as to how i can port my library created using Virtuoso to Genus for synthesis of HDL files? What all views need to be created for each cell?

    My final aim is to create a standard cell library that can be used for synthesis. As of now, I only have basic gates but I will add more cells later.
    As of now, I want to try out some synthesis using these basic gates.

    Thanks in advance!

  • in reply to iamKarthikBK

    Hi iamKarthikBK

    Please do not reply to old threads. This is against the rules for the forum. Please kindly start a new post for your issue.


    Best regards
    Quek

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