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  3. Importing spectre netlist with arrayed net names

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Importing spectre netlist with arrayed net names

Steven Mikes
Steven Mikes over 10 years ago

I have a netlist that I would like to import to a schematic. It contains subcircuits that have arrayed pins, e.g.

I0 (VDD VSS A\<2\> A\<1\> A\<0\>) myInstance

The schematic/symbol for myInstance in Cadence have the pins as  VDD VSS A<2:0>

I'm getting an error when importing that would look like this for this example:

Hush! For master cell 'refLib.myInstance:symbol' terminal order has less terminals than on instance. Expected: 5 Found: 3

How do I make the tool assign the terminals properly?

Thanks!

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  • Matth83
    Matth83 over 10 years ago

    Hi Steven,

    You'd need to modify your netlist so as to have the A terminals placed in a bus that match the CDF termOrder:

    I0 (VDD VSS A<2:0>) myInstance

    I myself use a script to do this (when extracting a layout to a .dspf spice-equivalent netlist, before I spice-it-in to get the extracted schematic).
    This script also proceeds to the '< >' and '( )' to=> '[ ]' changes wherever necessary in the spice netlist (usually where there's ':' or '#' right after the '>').

    I mention this because one might get the same "Expected:5 Found:3" error in case a line in the netlist is in the form:
    Xinst(1):Instance pin1 pin2 pin3 InstanceName
    The '()' brackets act like a separator and Spice-In would consider '1' and ':Instance' as 2 extra terminals. Whereas the following causes no problem:
    Xinst[1]:Instance pin1 pin2 pin3 InstanceName

    Regards,
    Matthieu

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    This reply (to a fairly old post) doesn't make much sense to me - you can't put (unexpanded) buses in a spectre netlist - so the example you give doesn't make sense (and is not legal syntax).

    If you want to use DSPF, you can do so nowadays using the dspf_include construct - which is available through Setup->Simulation Files in ADE. This can allow spectre to be able to map between the bus delimiters used on the schematic side and those used in the DSPF - and you also don't need to worry about pin ordering either.

    Regards,

    Andrew.

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  • Matth83
    Matth83 over 10 years ago

    Thanks Andrew for the insightful comment... still much to learn.
    I've replied to this old post because I was looking for some help on the topic not so long ago... finally I could find it myself, so I wished to share.
    I should have precised, I've used this step on an ASSURA QRC extracted .dspf netlist, which I wished to transform to an extracted schematic view using the Spice-In tool (File>Import>Spice...).

    Nevermind. I guess your way is more straight-forward, still I like having an extracted schematic view on which I can add or remove parasitics or replace circuits bits (eg. sizing MOS vs parasitics, etc...)

    True, I could also do this in the .dspf directly (well actually I do since I also have a procedure to disconnect parasitics on specified nets -commenting them out in the dspf- prior to the Spice-in) but could be risky in my view if you loose the overview.

    As for the buses, the Spice-in of a .dspf netlist doesn't work for me if I don't put pins into buses... what my script does is simply copying the termOrder in place of the extracted dspf .SUBCKT declaration at the beginning: 

        l_TermOrder = cdfGetCellCDF(ddGetObj(myLib myCell))->simInfo->spectre->termOrder
       TermOrder = ""
        foreach(w l_TermOrder TermOrder = strcat(TermOrder " " w))

        i = infile(myDspfNetlist) 

        while(gets(l i)
            if(pcreMatchp("^.SUBCKT " l) then ;# detected the .SUBCKT line
              fprintf(o strcat(".SUBCKT " cadr(parseString(l)) " " TermOrder "\n"))
       ;#... etc

    Regards,
    Matthieu

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