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  3. Importing spectre netlist with arrayed net names

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Importing spectre netlist with arrayed net names

Steven Mikes
Steven Mikes over 10 years ago

I have a netlist that I would like to import to a schematic. It contains subcircuits that have arrayed pins, e.g.

I0 (VDD VSS A\<2\> A\<1\> A\<0\>) myInstance

The schematic/symbol for myInstance in Cadence have the pins as  VDD VSS A<2:0>

I'm getting an error when importing that would look like this for this example:

Hush! For master cell 'refLib.myInstance:symbol' terminal order has less terminals than on instance. Expected: 5 Found: 3

How do I make the tool assign the terminals properly?

Thanks!

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    This reply (to a fairly old post) doesn't make much sense to me - you can't put (unexpanded) buses in a spectre netlist - so the example you give doesn't make sense (and is not legal syntax).

    If you want to use DSPF, you can do so nowadays using the dspf_include construct - which is available through Setup->Simulation Files in ADE. This can allow spectre to be able to map between the bus delimiters used on the schematic side and those used in the DSPF - and you also don't need to worry about pin ordering either.

    Regards,

    Andrew.

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    This reply (to a fairly old post) doesn't make much sense to me - you can't put (unexpanded) buses in a spectre netlist - so the example you give doesn't make sense (and is not legal syntax).

    If you want to use DSPF, you can do so nowadays using the dspf_include construct - which is available through Setup->Simulation Files in ADE. This can allow spectre to be able to map between the bus delimiters used on the schematic side and those used in the DSPF - and you also don't need to worry about pin ordering either.

    Regards,

    Andrew.

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