Creating a CNTFET model in cadence using veriloga

I want to model a cntfet in cadence using veriloga. I used the veriloga code (nano.stanford.edu/stanford-cnfet-model-verilog). I followed these steps to create the cntfet model-

1. I created a new veriloga cell view and edited the veriloga.va by copying the code of NCNTFET_L3.va. I also added the fles NCNFET_L2.va, NCNCNT_L3.va and parameters.vams in the veriloga directory created.

2. I created a symbol from the veriloga cell view (create->cellview->from cellview).

3. Now I opened a new schematic and used this symbol to implement a simple circuit. I was not able to select from schematic for plotting the outputs and encountered the error - 

ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corrupt or may not be produced at all. 

To generate correct netlist, fix the errors and re-netlist.
      ...unsuccessful.

What and where could be the problem? Kindly look into this and help me out.