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Loading a netlist for simulation

MohamedMohie

Dear Expert,

I'm simulating a big design "FPGA tile" and I'm looking for calculating the leakage power, so I found in the simulation directory the "input.scs" file which is gets simulated by spectre in ADE L . So, I decided to change the gate voltage in this file to all transistors to be zero so I can calculate the leakage current, but now, I have a new "say input1.scs" file with the gate voltage of zero.

My question is, How can I instruct spectre "or ADE L " to simulate this new .scs file ? in other words, If I have a standalone netlist for example, how could I upload it to the simulator and enforce the simulator to only consider this netlist, Not to netlist the design and RUN but itself but just use the loaded netlist and run?

Appreciate your help.

Thanks

Parents

  • Thanks a lot, Tom for your reply.

    However, I'm in kind of doubt regarding the procedure I mentioned to calculate the leakage power.

    Actually, what I'm doing is, I open the netlist, modify every M's second attribute "for ex. M0 (D G S B)" and make every G is 0. I suspect that this is just renaming to the net not forcing a value of zero voltage on the M0 transistor's gate .. is that correct?

    And if it's correct, what could be the best procedure to follow in order to calculate the leakage current/power in a big design such as the one I'm running now "FPGA tile"? ... I simply thought of making every gate voltage of all transistors in the design to be zero voltage "by modifying the netlist the way I just mentioned" to calculate the power drawn from the Vdc while all transistors are off. May be there's  much simpler/reasonable way to do so. Any help would be very appreciated.

    It's worth to mention that I'm new to Cadence so you might find my questions some how trivial.

    I'm using Cadence 6.1.5

    Thank you

Reply

  • Thanks a lot, Tom for your reply.

    However, I'm in kind of doubt regarding the procedure I mentioned to calculate the leakage power.

    Actually, what I'm doing is, I open the netlist, modify every M's second attribute "for ex. M0 (D G S B)" and make every G is 0. I suspect that this is just renaming to the net not forcing a value of zero voltage on the M0 transistor's gate .. is that correct?

    And if it's correct, what could be the best procedure to follow in order to calculate the leakage current/power in a big design such as the one I'm running now "FPGA tile"? ... I simply thought of making every gate voltage of all transistors in the design to be zero voltage "by modifying the netlist the way I just mentioned" to calculate the power drawn from the Vdc while all transistors are off. May be there's  much simpler/reasonable way to do so. Any help would be very appreciated.

    It's worth to mention that I'm new to Cadence so you might find my questions some how trivial.

    I'm using Cadence 6.1.5

    Thank you

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