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Loading a netlist for simulation

MohamedMohie

Dear Expert,

I'm simulating a big design "FPGA tile" and I'm looking for calculating the leakage power, so I found in the simulation directory the "input.scs" file which is gets simulated by spectre in ADE L . So, I decided to change the gate voltage in this file to all transistors to be zero so I can calculate the leakage current, but now, I have a new "say input1.scs" file with the gate voltage of zero.

My question is, How can I instruct spectre "or ADE L " to simulate this new .scs file ? in other words, If I have a standalone netlist for example, how could I upload it to the simulator and enforce the simulator to only consider this netlist, Not to netlist the design and RUN but itself but just use the loaded netlist and run?

Appreciate your help.

Thanks

  • In the same directory in which you found the input.scs file, there should be a file called runSimulation.  This will have the spectre command that was used when you initially ran the simulation in ADE L.  Edit this file to reference input1.scs and run that command.

  • Thanks a lot, Tom for your reply.

    However, I'm in kind of doubt regarding the procedure I mentioned to calculate the leakage power.

    Actually, what I'm doing is, I open the netlist, modify every M's second attribute "for ex. M0 (D G S B)" and make every G is 0. I suspect that this is just renaming to the net not forcing a value of zero voltage on the M0 transistor's gate .. is that correct?

    And if it's correct, what could be the best procedure to follow in order to calculate the leakage current/power in a big design such as the one I'm running now "FPGA tile"? ... I simply thought of making every gate voltage of all transistors in the design to be zero voltage "by modifying the netlist the way I just mentioned" to calculate the power drawn from the Vdc while all transistors are off. May be there's  much simpler/reasonable way to do so. Any help would be very appreciated.

    It's worth to mention that I'm new to Cadence so you might find my questions some how trivial.

    I'm using Cadence 6.1.5

    Thank you

  • Assuming 0 is your global ground (which it normally would be if the netlist was produced by ADE), then connecting the gates of the NMOS transistors to 0 would cause 0V on the gate. However, wouldn't you want your PMOS devices to be connected to VDD?

    Andrew.

  • Thanks Andrew for your reply.

    I actually realized that some parts of my design contains drains and sources of transistors that are connected to gates of successive or preceding transistors, so it might be illogical to do so "I mean to replace every G in M0 (D G S B) with 0" .. and Thanks for bringing up the point of the PMOS, yeah definitely my design has PMOS and needs to be connected to VDD, I slipped it!

    I'm now stuck at point that I really don't know a smart or doable way to calculate the leakage current/power in a big design like mine, and I really appreciate any advise or help regarding this.

    Thanks

  • Generally speaking you'd measure the leakage by simulating in a state where nothing should be active, rather than artificially turning all devices off. I can't think of a good way to force all devices to be off as that's a rather odd thing to do...
  • Hi Andrew, I'm afraid I didn't get exactly what you mean by "state where nothing should be active" .. can you give me an example if you please? ... Thanks
  • What I mean is ensuring that the circuit is in a state where nothing is active - it's not switching, things are in powerdown mode (or similar). Generally speaking one is most concerned about leakage power when the circuit is supposed to be inactive and powered down; if it is active, it's inevitably consuming current. If it's in some kind of standby mode, the circuit shouldn't be consuming any significant current - this will eat into your battery life if it actually does.

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