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  3. Loading a netlist for simulation

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Loading a netlist for simulation

MohamedMohie
MohamedMohie over 10 years ago

Dear Expert,

I'm simulating a big design "FPGA tile" and I'm looking for calculating the leakage power, so I found in the simulation directory the "input.scs" file which is gets simulated by spectre in ADE L . So, I decided to change the gate voltage in this file to all transistors to be zero so I can calculate the leakage current, but now, I have a new "say input1.scs" file with the gate voltage of zero.

My question is, How can I instruct spectre "or ADE L " to simulate this new .scs file ? in other words, If I have a standalone netlist for example, how could I upload it to the simulator and enforce the simulator to only consider this netlist, Not to netlist the design and RUN but itself but just use the loaded netlist and run?

Appreciate your help.

Thanks

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  • MohamedMohie
    MohamedMohie over 10 years ago

    Thanks Andrew for your reply.

    I actually realized that some parts of my design contains drains and sources of transistors that are connected to gates of successive or preceding transistors, so it might be illogical to do so "I mean to replace every G in M0 (D G S B) with 0" .. and Thanks for bringing up the point of the PMOS, yeah definitely my design has PMOS and needs to be connected to VDD, I slipped it!

    I'm now stuck at point that I really don't know a smart or doable way to calculate the leakage current/power in a big design like mine, and I really appreciate any advise or help regarding this.

    Thanks

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  • MohamedMohie
    MohamedMohie over 10 years ago

    Thanks Andrew for your reply.

    I actually realized that some parts of my design contains drains and sources of transistors that are connected to gates of successive or preceding transistors, so it might be illogical to do so "I mean to replace every G in M0 (D G S B) with 0" .. and Thanks for bringing up the point of the PMOS, yeah definitely my design has PMOS and needs to be connected to VDD, I slipped it!

    I'm now stuck at point that I really don't know a smart or doable way to calculate the leakage current/power in a big design like mine, and I really appreciate any advise or help regarding this.

    Thanks

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