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LVS Matching error

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Hi everybody
I'm using Diva from Cadence to run LVS.
I get many nets and devices mismatch when running an LVS. This is due to M factor of mos transistor, and also because I draw my MOS transistors in Layout using multifingered design. I thought LVS didn't recognize parallel device, but
I checked DivaLVS.rul file and parallel simplification seems to be set by permuteDevice statement. (permuteDevice parallel "nfet")......)
Have anyone been faced to this problem and could help me resolve this???

any help will be very appreciated thanks!!!!


Originally posted in cdnusers.org by isazul
Parents

  • Not sure why you had to put the rule file into a Word document - a text file would be sufficient - just makes it harder to read...

    Anyway, from a quick glance through the file, it appears to be checking and combining m.

    So I would suggest you check with whoever you get the design kit and rules from, or contact Cadence customer support. Most likely they'll need to see the design data to see what's wrong - it's hard to figure it out without seeing the whole picture.

    There's no fundamental tool reason why this shouldn't work. You might want to also check that the netlists you're getting for both the schematic and layout have the parameters w,l and m in them for these transistors (you can access these netlists from the LVS form).

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
Reply

  • Not sure why you had to put the rule file into a Word document - a text file would be sufficient - just makes it harder to read...

    Anyway, from a quick glance through the file, it appears to be checking and combining m.

    So I would suggest you check with whoever you get the design kit and rules from, or contact Cadence customer support. Most likely they'll need to see the design data to see what's wrong - it's hard to figure it out without seeing the whole picture.

    There's no fundamental tool reason why this shouldn't work. You might want to also check that the netlists you're getting for both the schematic and layout have the parameters w,l and m in them for these transistors (you can access these netlists from the LVS form).

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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