LVS Matching error

Well, it rather depends on what the function that is being used in the permuteDevice() is doing. This will be a SKILL function, and it needs to take into account the w, l and m of the transistors being combined appropriately, otherwise you'll get parameter mismatches. If it only looks at w and l, then it's not going to work properly...

Regards,

Andrew.

Originally posted in cdnusers.org by adbeckett

This is the DivaLVS rules file I  use.
 Are the pemuteDevice statement wrong??

Thanks

Originally posted in cdnusers.org by isazul

Not sure why you had to put the rule file into a Word document - a text file would be sufficient - just makes it harder to read...

Anyway, from a quick glance through the file, it appears to be checking and combining m.

So I would suggest you check with whoever you get the design kit and rules from, or contact Cadence customer support. Most likely they'll need to see the design data to see what's wrong - it's hard to figure it out without seeing the whole picture.

There's no fundamental tool reason why this shouldn't work. You might want to also check that the netlists you're getting for both the schematic and layout have the parameters w,l and m in them for these transistors (you can access these netlists from the LVS form).

Regards,

Andrew.

Originally posted in cdnusers.org by adbeckett

I've encountered this problem as well. I've looked at various forums and Design-Kit rule files from a variety of fabs but none were able to solve this problem. So I've thought long and hard about this problem and I've come up with a solution. The thing is, Diva LVS only combines 2 transistors at a time. The way most rule files instruct this combination is by adding the widths and averaging the lengths, after multiplying the m factor into the width. If one looks carefully at this formula from a mathematical perspective, you'll see that it's only accurate when both transistor have equal lengths. The mathematical error only appears when there are 3 or more transistors being combined. Take for instance 3 transistors T1,T2,T3 with W1/L1 , W2/L2 and W3/L3 respectively. Diva will first combine T12 = T1 & T2 before combining T12 & T3. If you do the maths, you'll see that if the extracted view is combined in a different order than the schematic view there will be a mismatch. --->Try combining T31 = T3 & T1 and then T31 & T2 and compare it with your previous answer ;-) To do this correctly, one must have a look at the 1st order equation of a MOSFET: Id = (W/L)k(Vgs-Vt)^2 When transistors are in parallel their drain currents add up and they share the same Vgs voltage. So, Id_par = Id1 + Id2 + ... + Idn = (W1/L1 + W1/L2 + ... + Wn/Ln)k(Vgs-Vt)^2 and therefore W_par/L_par = W1/L1 + W1/L2 + ... + Wn/Ln ... (1) Another thing to remember is that their areas add up too: W_par*L_par = W1*L1 + W2*L2 + ... + Wn*Ln ... (2) If you say (1) * (2) you get W_par ^2 = (W1/L1 + W1/L2 + ... + Wn/Ln)/(W1*L1 + W2*L2 + ... + Wn*Ln) and I WON'T solve L_par for you! ;-) But, I'll give you the equations from my parallelMOS procedure: parMos->l = sqrt( (m1->w*m1->m*m1->l + m2->w*m2->m*m2->l)/(m1->w*m1->m/m1->l + m2->w*m2->m/m2->l) ) parMos->w = sqrt( (m1->w*m1->m*m1->l + m2->w*m2->m*m2->l)*(m1->w*m1->m/m1->l + m2->w*m2->m/m2->l) ) parMos->m = 1.0 Regards, Tjaart P.S. I've used this equation in my rule files a number of times. It seems to work very well, but what I've seen is that there are still some transistors that can't be resolved. This is a very special case. It happens when you have 2 or more transistors with pairs that look similar but have different size. This mostly happens with spare logic. For instance 2 inverters of a different size, with both supplies and inputs connected to the same nodes & with floating outputs, would usually give a logical mismatch. Enjoy!

Rather hard to read your append because of the line wrap, but there's a much simpler way to solve this - rather than combining and keeping just w and l, keep track of m as well when you combine parallel mos. Here's some old code (not tested for a long time, but you should get the idea)

procedure(parallelMOS(m1 m2) 
    let((mt mult1 mult2 lmult1 lmult2) 
	mt = ncons(nil)
	mt->m = nil 
	mt->W = nil 
	mt->L = nil
	;----------------------------------------------------------------
	; get multipliers
	;----------------------------------------------------------------
	if(m1->m then
	    mult1 = m1->m
	else
	    mult1 = 1
	) 
	if(m2->m then
	    mult2 = m2->m
	else
	    mult2 = 1
	) 
	;----------------------------------------------------------------
	; get the length multipliers - this is so that the average length
	; can be calculated correctly
	;----------------------------------------------------------------
	if(m1->lm then
	    lmult1 = m1->lm
	else
	    lmult1 = 1
	) 
	if(m2->lm then
	    lmult2 = m2->lm
	else
	    lmult2 = 1
	) 
	;----------------------------------------------------------------
	; Combine widths - try to preserve multipliers if possible
	;----------------------------------------------------------------
	if(m1->W && m2->W then
	    if(m1->W == m2->W && m1->L == m2->L then
		mt->W = m1->W
		mt->m = mult1 + mult2
	    else
		mt->W = m1->W * mult1 + m2->W * mult2
		mt->m = 1
	    )
	)
	;----------------------------------------------------------------
	; Combine lengths
	;----------------------------------------------------------------
	when(m1->L && m2->L
	    mt->L = (m1->L * lmult1 + m2->L * lmult2) / (lmult1 + lmult2)
	    mt->lm = lmult1 + lmult2
	) 
	mt
    )
)

Note of course it means that you'd need to take into account the m factor in the comparison function - you could multiply W by m then. Or you could choose (Diva allows this) to reject combination of parallel devices which are not the same W and L. That's quite a good idea - and then you could also check that the m factors match between schematic and layout - it depends on how rigid you are about allowing folding of W into multiple fingers - for good analog layout, I would always say that you should not divide the W differently at layout time, because then delta-W effects mean that your layout doesn't really match the schematic, and that may mess up the behaviour of the design (for critical, matched transistor, circuits).

Regards,

Andrew.