LVS Matching error

I've encountered this problem as well. I've looked at various forums and Design-Kit rule files from a variety of fabs but none were able to solve this problem. So I've thought long and hard about this problem and I've come up with a solution. The thing is, Diva LVS only combines 2 transistors at a time. The way most rule files instruct this combination is by adding the widths and averaging the lengths, after multiplying the m factor into the width. If one looks carefully at this formula from a mathematical perspective, you'll see that it's only accurate when both transistor have equal lengths. The mathematical error only appears when there are 3 or more transistors being combined. Take for instance 3 transistors T1,T2,T3 with W1/L1 , W2/L2 and W3/L3 respectively. Diva will first combine T12 = T1 & T2 before combining T12 & T3. If you do the maths, you'll see that if the extracted view is combined in a different order than the schematic view there will be a mismatch. --->Try combining T31 = T3 & T1 and then T31 & T2 and compare it with your previous answer ;-) To do this correctly, one must have a look at the 1st order equation of a MOSFET: Id = (W/L)k(Vgs-Vt)^2 When transistors are in parallel their drain currents add up and they share the same Vgs voltage. So, Id_par = Id1 + Id2 + ... + Idn = (W1/L1 + W1/L2 + ... + Wn/Ln)k(Vgs-Vt)^2 and therefore W_par/L_par = W1/L1 + W1/L2 + ... + Wn/Ln ... (1) Another thing to remember is that their areas add up too: W_par*L_par = W1*L1 + W2*L2 + ... + Wn*Ln ... (2) If you say (1) * (2) you get W_par ^2 = (W1/L1 + W1/L2 + ... + Wn/Ln)/(W1*L1 + W2*L2 + ... + Wn*Ln) and I WON'T solve L_par for you! ;-) But, I'll give you the equations from my parallelMOS procedure: parMos->l = sqrt( (m1->w*m1->m*m1->l + m2->w*m2->m*m2->l)/(m1->w*m1->m/m1->l + m2->w*m2->m/m2->l) ) parMos->w = sqrt( (m1->w*m1->m*m1->l + m2->w*m2->m*m2->l)*(m1->w*m1->m/m1->l + m2->w*m2->m/m2->l) ) parMos->m = 1.0 Regards, Tjaart P.S. I've used this equation in my rule files a number of times. It seems to work very well, but what I've seen is that there are still some transistors that can't be resolved. This is a very special case. It happens when you have 2 or more transistors with pairs that look similar but have different size. This mostly happens with spare logic. For instance 2 inverters of a different size, with both supplies and inputs connected to the same nodes & with floating outputs, would usually give a logical mismatch. Enjoy!

I've encountered this problem as well. I've looked at various forums and Design-Kit rule files from a variety of fabs but none were able to solve this problem. So I've thought long and hard about this problem and I've come up with a solution. The thing is, Diva LVS only combines 2 transistors at a time. The way most rule files instruct this combination is by adding the widths and averaging the lengths, after multiplying the m factor into the width. If one looks carefully at this formula from a mathematical perspective, you'll see that it's only accurate when both transistor have equal lengths. The mathematical error only appears when there are 3 or more transistors being combined. Take for instance 3 transistors T1,T2,T3 with W1/L1 , W2/L2 and W3/L3 respectively. Diva will first combine T12 = T1 & T2 before combining T12 & T3. If you do the maths, you'll see that if the extracted view is combined in a different order than the schematic view there will be a mismatch. --->Try combining T31 = T3 & T1 and then T31 & T2 and compare it with your previous answer ;-) To do this correctly, one must have a look at the 1st order equation of a MOSFET: Id = (W/L)k(Vgs-Vt)^2 When transistors are in parallel their drain currents add up and they share the same Vgs voltage. So, Id_par = Id1 + Id2 + ... + Idn = (W1/L1 + W1/L2 + ... + Wn/Ln)k(Vgs-Vt)^2 and therefore W_par/L_par = W1/L1 + W1/L2 + ... + Wn/Ln ... (1) Another thing to remember is that their areas add up too: W_par*L_par = W1*L1 + W2*L2 + ... + Wn*Ln ... (2) If you say (1) * (2) you get W_par ^2 = (W1/L1 + W1/L2 + ... + Wn/Ln)/(W1*L1 + W2*L2 + ... + Wn*Ln) and I WON'T solve L_par for you! ;-) But, I'll give you the equations from my parallelMOS procedure: parMos->l = sqrt( (m1->w*m1->m*m1->l + m2->w*m2->m*m2->l)/(m1->w*m1->m/m1->l + m2->w*m2->m/m2->l) ) parMos->w = sqrt( (m1->w*m1->m*m1->l + m2->w*m2->m*m2->l)*(m1->w*m1->m/m1->l + m2->w*m2->m/m2->l) ) parMos->m = 1.0 Regards, Tjaart P.S. I've used this equation in my rule files a number of times. It seems to work very well, but what I've seen is that there are still some transistors that can't be resolved. This is a very special case. It happens when you have 2 or more transistors with pairs that look similar but have different size. This mostly happens with spare logic. For instance 2 inverters of a different size, with both supplies and inputs connected to the same nodes & with floating outputs, would usually give a logical mismatch. Enjoy!