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  3. Need information regarding Transient Analysis

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Need information regarding Transient Analysis

jdp721
jdp721 over 10 years ago

Hi.

I have a particular circuit block (to be precise, a switched capacitor 2nd order integrator), say block-A, which when transient simulated in Virtuoso ADE gives stable desired outputs.

Now, in the same schematic, when I am placing another circuit block-B (a regenerative comparator), without even any connection between the two blocks A and B, the transient output of block-A is showing ringing/oscillations !


It seems so strange that without any interaction between A and B, the output of A is getting affected due to the mere presence of B in the sch! Can anyone please explain this phenomenon?

Is it something like the presence of B is causing the simulator to decipher the ringing in A, which went otherwise unseen?!?

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  • ShawnLogan
    ShawnLogan over 10 years ago

    Dear jpd721,

    > It seems so strange that without any interaction between A and B, the output of A

    > is getting affected due to the mere presence of B in the sch! Can anyone please explain this phenomenon?

    Have you examine the simulator accuracy settings in the two simulations? Specifically, the addition of circuit B in your simulation may result in a smaller integration step than is used when simulating circuit A alone. As a result, there may be a difference in the relative performance of circuit A. You might try forcing a specific errpreset and maxstep when simulating A alone and A+B. For example, you might set errpreset to "moderate" and set "maxstep" to 1 ps (I don't know if those are the right settings for your circuit - but are examples) and then compare the responses of circuit A. If you do not set maxstep, its default value is dependent on the length of the simulation. If the simulation time of circuit A+B is different than just circuit A, its default value will be different in the simulations.

    I hope this helps,

    Shawn

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  • Frank Wiedmann
    Frank Wiedmann over 10 years ago

    I also think that different timestep sizes are the most likely reason for the different simulation results you are seeing. However, you also might want to check if you have accidentally created a connection by name between your blocks A and B by labeling wires with the same name.

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