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Need information regarding Transient Analysis

jdp721

Hi.

I have a particular circuit block (to be precise, a switched capacitor 2nd order integrator), say block-A, which when transient simulated in Virtuoso ADE gives stable desired outputs.

Now, in the same schematic, when I am placing another circuit block-B (a regenerative comparator), without even any connection between the two blocks A and B, the transient output of block-A is showing ringing/oscillations !


It seems so strange that without any interaction between A and B, the output of A is getting affected due to the mere presence of B in the sch! Can anyone please explain this phenomenon?

Is it something like the presence of B is causing the simulator to decipher the ringing in A, which went otherwise unseen?!?

Parents

  • I also think that different timestep sizes are the most likely reason for the different simulation results you are seeing. However, you also might want to check if you have accidentally created a connection by name between your blocks A and B by labeling wires with the same name.

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  • I also think that different timestep sizes are the most likely reason for the different simulation results you are seeing. However, you also might want to check if you have accidentally created a connection by name between your blocks A and B by labeling wires with the same name.

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