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VerilogA model with passive components in the transient analysis

Sali

Dear all,

I have a question and I'll appreciate any help.

I'm using Virtuoso to simulate a circuit containing many VerilogA models connected to  number of RC circuits, and current sources, the final output of the circuit is a voltage in a sigmoidal form, if I apply input 1 to the circuit the output should be + (positive part of the sigmoidal)  , for input 2 the output should be - (negative part of the sigmoidal), what I want to do is to apply the input then check the final output if the result is wrong I feedback the output to use it in the VerilogA model again to update some variables,  my question is how to set/ control the number of iterations in order for the simulation to stop once I get the correct output, in other words I'm seeing the whole circuit as one unit (VerilogA + passive components and sources) the input will pass the whole circuit then fedback to the verilogA models , this is count as a one iteration, so how to control that?

Thank you in advance,

Sali

Parents

  • Hi Andrew,

    Could you please tell me how to upload an image?

    In the following sketch which is part of my circuit, the VerilogA block in the left side is generating a current Iout which becomes the input of the second part of the circuit, there is an equation inside the VerilogA block that measures a certain error inside an if statement, if that error > a certain value I increase/decrease the current Iout, then the Vout (final output in the right side )is fedback to that VerilogA block to repeat again the same error measurement, the simulation should be stopped once the error reaches a very small value for example 1e-50, how can I control that?

    Thank you in advance,

    Sali

Reply

  • Hi Andrew,

    Could you please tell me how to upload an image?

    In the following sketch which is part of my circuit, the VerilogA block in the left side is generating a current Iout which becomes the input of the second part of the circuit, there is an equation inside the VerilogA block that measures a certain error inside an if statement, if that error > a certain value I increase/decrease the current Iout, then the Vout (final output in the right side )is fedback to that VerilogA block to repeat again the same error measurement, the simulation should be stopped once the error reaches a very small value for example 1e-50, how can I control that?

    Thank you in advance,

    Sali

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