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VerilogA model with passive components in the transient analysis

Sali

Dear all,

I have a question and I'll appreciate any help.

I'm using Virtuoso to simulate a circuit containing many VerilogA models connected to  number of RC circuits, and current sources, the final output of the circuit is a voltage in a sigmoidal form, if I apply input 1 to the circuit the output should be + (positive part of the sigmoidal)  , for input 2 the output should be - (negative part of the sigmoidal), what I want to do is to apply the input then check the final output if the result is wrong I feedback the output to use it in the VerilogA model again to update some variables,  my question is how to set/ control the number of iterations in order for the simulation to stop once I get the correct output, in other words I'm seeing the whole circuit as one unit (VerilogA + passive components and sources) the input will pass the whole circuit then fedback to the verilogA models , this is count as a one iteration, so how to control that?

Thank you in advance,

Sali

Parents

  • Dear all,

    Regarding my previous question , all these blocks in the circuit are VerilogA blocks, I need the signal from the left side to pass through all the blocks to get the output in the right side, actually I have two data files inside the block , which is in the left side, I want to read the first file only to get the output in the right side then go back again to the same verilogA block in the left side to read the second file to get the output related to it, then I use both results to calculate a certain error, then use this error to increase/decrease some variables inside the block and repeat the same steps again until the error is minimized to a certain value, can I control the simulation to do that?

    If not, is there a way to save the same circuit under another name and past it beside the original one and apply the second file as an input to it and change the relevant variables without affecting the same variables in the original circuit? or I should start to save as all the VerilogA blocks under another names first before start the simulation using this way? since the figure I attach is only a small portion of my big circuit.

    I'll appreciate any help.

    Thank you in advance,

    Sali

Reply

  • Dear all,

    Regarding my previous question , all these blocks in the circuit are VerilogA blocks, I need the signal from the left side to pass through all the blocks to get the output in the right side, actually I have two data files inside the block , which is in the left side, I want to read the first file only to get the output in the right side then go back again to the same verilogA block in the left side to read the second file to get the output related to it, then I use both results to calculate a certain error, then use this error to increase/decrease some variables inside the block and repeat the same steps again until the error is minimized to a certain value, can I control the simulation to do that?

    If not, is there a way to save the same circuit under another name and past it beside the original one and apply the second file as an input to it and change the relevant variables without affecting the same variables in the original circuit? or I should start to save as all the VerilogA blocks under another names first before start the simulation using this way? since the figure I attach is only a small portion of my big circuit.

    I'll appreciate any help.

    Thank you in advance,

    Sali

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