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  3. *Warning* (DB-220704) : The Pcell super master : lf150rf_lib...

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*Warning* (DB-220704) : The Pcell super master : lf150rf_lib/ResistorUnit/layout is not a SKILL super master

Sss19
Sss19 over 10 years ago

Hello,

I have recently installed IC615 and using LFoundry 150nm tech file. While trying to generate the layout from Schematic, I get the following error and in the layout, I can only see a while square (no layers) in place of capacitor and MOS layout. However, the inductor layout appears normal. Can someone tell me how to resolve the issue.

*Warning* (DB-220704) : The Pcell super master : lf150rf_lib/ResistorUnit/layout is not a SKILL super master.

The usage of non-SKILL Pcells in Virtuoso is not a supported feature.

 

Can someone help me how to resolve the issue.

Regards,

 

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    The way to resolve this is to contact the foundry and ask them to provide native SKILL pcells.

    The warning is given because there is no support for non-SKILL pcells; any issues that might occur because of using them - bugs, tool stability etc - cannot be supported by Cadence because we do not have access to the foreign pcell evaluators and associated source code. They might work, but there is no testing of this flow and it presents problems with providing testcases to Cadence. Also, some parts of the tool functionality are not available if you use non-SKILL pcells (e.g. some of the VLS GXL functionality).

    Regards,

    Andrew.

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  • uschi
    uschi over 10 years ago

    Hi,

    LFoundry uses PyCells. Included in their PDK are the necessary plugins. If you followed the installation instructions you will have environment variables CNI_ROOT and CNI_PLAT_ROOT. These indicate (amongst others) if you are using 32bit or 64bit. Make sure that your Virtuoso Layout Editor is set to the same value. You can test your VLE for example  with this command:  "layout -debug3264" . If you have different width, than your PyCells will not work.

    Ignore the "Warning". It will also appear if your setup is correct.

    Uli

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  • Andrew Beckett
    Andrew Beckett over 10 years ago

    uschi said:
    Ignore the "Warning". It will also appear if your setup is correct.

    You should not ignore the warning. You should  take notice of the warning, because it is telling you that this is not supported by Cadence. If you're happy with that risk, then fair enough, but you should take notice of it.

    Kind Regards,

    Andrew.

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  • Sss19
    Sss19 over 10 years ago

    Thank you all for your replies. I have checked the cshrc file with the help of IT Manager and we found that we already have PyCell Studio to run the Non SKILL Pcells but some paths were not correct. We corrected them and now I can see the layout layers. The thing is, I can see that some warnings still persist and they were there before the changes as well. They are like

    *WARNING* (LX-2003): Cannot create instance terminal on layout instance 'IM25' because the instance master 'lf150_rflib/nmosrf_hs_4/layout''does not have a corresponding terminal 'B'

    Similar message was appearing for other terminals of the MOS but now they have disappeared. Any idea of what this is indicating??

    Regards,

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  • ColinSutlieff
    ColinSutlieff over 10 years ago

    Hi,

    As Andrew mentioned in an earlier post, the warnings are an indication that you may have issues.

    And here is the first one.

     I can see that this is an XL warning message. You are using VLS-XL and having connectivity issues with a layout generated from a PyCell.

    I am guessing that this is a bulk terminal and is not physically defined in the layout.

    The extractor can support non-physical terminals but it needs to be handled in the P-cell.

    But as it isn't a p-cell there is not much extra that can be done on the Cadence side. Perhaps you should contact with your PDK supplier or, whoever maintains the Pycells.

     

    Colin

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