Stats

  • Locked Locked
  • Replies 5
  • Subscribers 126
  • Views 4237
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

*Warning* (DB-220704) : The Pcell super master : lf150rf_lib/ResistorUnit/layout is not a SKILL super master

Sss19

Hello,

I have recently installed IC615 and using LFoundry 150nm tech file. While trying to generate the layout from Schematic, I get the following error and in the layout, I can only see a while square (no layers) in place of capacitor and MOS layout. However, the inductor layout appears normal. Can someone tell me how to resolve the issue.

*Warning* (DB-220704) : The Pcell super master : lf150rf_lib/ResistorUnit/layout is not a SKILL super master.

The usage of non-SKILL Pcells in Virtuoso is not a supported feature.

 

Can someone help me how to resolve the issue.

Regards,

 

Parents

  • Hi,

    As Andrew mentioned in an earlier post, the warnings are an indication that you may have issues.

    And here is the first one.

     I can see that this is an XL warning message. You are using VLS-XL and having connectivity issues with a layout generated from a PyCell.

    I am guessing that this is a bulk terminal and is not physically defined in the layout.

    The extractor can support non-physical terminals but it needs to be handled in the P-cell.

    But as it isn't a p-cell there is not much extra that can be done on the Cadence side. Perhaps you should contact with your PDK supplier or, whoever maintains the Pycells.

     

    Colin

Reply

  • Hi,

    As Andrew mentioned in an earlier post, the warnings are an indication that you may have issues.

    And here is the first one.

     I can see that this is an XL warning message. You are using VLS-XL and having connectivity issues with a layout generated from a PyCell.

    I am guessing that this is a bulk terminal and is not physically defined in the layout.

    The extractor can support non-physical terminals but it needs to be handled in the P-cell.

    But as it isn't a p-cell there is not much extra that can be done on the Cadence side. Perhaps you should contact with your PDK supplier or, whoever maintains the Pycells.

     

    Colin

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.