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Unable to generate Proper Layouts

SHEKHARvnit

Hi,

     Recently we upgraded to IC6.1.5-64b, in the older version of Cadence we were using UMC 180nm Pdk, after the upgrade we are not able to use this package effectively. When we generate Layout for UMC transistors from schematic , the Layout obtained does not follow design rules , such as placement of contact, size of contact, spacing between contacts, length of polysilicon,  width of Poly etc.  We are not able to debug this issue. I have attached the image of PMOS and NMOS layout for  reference.

Displaying pmos and nmos layout.png

 

Parents
  • Thanks for the picture. This probably means that the pcell code is making some invalid assumption which has resulted in it working correctly in the past, but that assumption is no longer valid. I suspect it's highly likely that a newer version of the PDK is available which addresses this issue, so as I said, you need to contact the supplier of the PDK for a fixed version. It's undoubtedly going to need a fix to the PDK whatever happens.
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  • Thanks for the picture. This probably means that the pcell code is making some invalid assumption which has resulted in it working correctly in the past, but that assumption is no longer valid. I suspect it's highly likely that a newer version of the PDK is available which addresses this issue, so as I said, you need to contact the supplier of the PDK for a fixed version. It's undoubtedly going to need a fix to the PDK whatever happens.
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