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Unable to generate Proper Layouts

Hi,

Recently we upgraded to IC6.1.5-64b, in the older version of Cadence we were using UMC 180nm Pdk, after the upgrade we are not able to use this package effectively. When we generate Layout for UMC transistors from schematic , the Layout obtained does not follow design rules , such as placement of contact, size of contact, spacing between contacts, length of polysilicon, width of Poly etc. We are not able to debug this issue. I have attached the image of PMOS and NMOS layout for reference.

Displaying pmos and nmos layout.png

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Andrew Beckett over 10 years ago

I have no access to this PDK, so can't help. Shouldn't you ask the PDK provider? Not all PDKs are structured the same, so it's best to request documentation from whoever provided the PDK (presumably UMC).
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Andrew Beckett over 10 years ago

I have no access to this PDK, so can't help. Shouldn't you ask the PDK provider? Not all PDKs are structured the same, so it's best to request documentation from whoever provided the PDK (presumably UMC).
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