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Connections between Bulk or gate and source for a PMOS

Leof

Hi,

I am new to cadence. I have a doubt. generally in PMOS gate is connected to source. IN my case gate is connected directly to vdd, and the other side of gate is connected to the output. In other words, I do not have free pin  to connect to the source. We connect it to reduce body effect. I came to know that we connect to ground in this case.

I am here by sending the schematic. Could you let me know how do I connect to the source for the second transistor p1

Thank you

Regards

Leo

Parents
  • MN0 and MN1 are "pull-down" transistors, so if A or B are 'high' then Out is Low, and MP1 and p1 are "pull-up" transistors, so when A and B are both 'low', Out is pulled 'high'. This is a NOR gate, as I suspected. By the way, if p1 is the same kind of device as MP1 then they should be in the same orientation; one of them looks to be upside-down (not sure which, since I don't "know" this symbol)... Regards, Lawrence.
Reply
  • MN0 and MN1 are "pull-down" transistors, so if A or B are 'high' then Out is Low, and MP1 and p1 are "pull-up" transistors, so when A and B are both 'low', Out is pulled 'high'. This is a NOR gate, as I suspected. By the way, if p1 is the same kind of device as MP1 then they should be in the same orientation; one of them looks to be upside-down (not sure which, since I don't "know" this symbol)... Regards, Lawrence.
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