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Connections between Bulk or gate and source for a PMOS

Leof

Hi,

I am new to cadence. I have a doubt. generally in PMOS gate is connected to source. IN my case gate is connected directly to vdd, and the other side of gate is connected to the output. In other words, I do not have free pin  to connect to the source. We connect it to reduce body effect. I came to know that we connect to ground in this case.

I am here by sending the schematic. Could you let me know how do I connect to the source for the second transistor p1

Thank you

Regards

Leo

  • Hi Leo,

    I think that you have a few things mixed up.  The Bulk of p1 is connected to vdd!, the gate is connected to pin B, the source is connected to the drain of MP1 and the drain of p1 appears to be connected to net/pin "Out".  I would guess that this is a NOR configuration with the P-channel devices in series and the N-channel devices effectively in parallel?

    However, I would not expect the net between p1 source and MP1 drain to be "B" - it should be an internal net, different to "B" if this is indeed a NOR gate...

    Hopefully this helps?

    Regards,

    Lawrence.

  • I really do not understand. I have sent only half of the schematic. Here is my full schematic.

  • I'm not sure I understand your question. Don't think this is anything to do with "Cadence" (there's no tool called "Cadence"), but simply to do with the design - but it's very unclear from your original question what your issue actually is? The circuit looks like a simple nor gate, as Lawrence says. Nothing unusual about it.
  • MN0 and MN1 are "pull-down" transistors, so if A or B are 'high' then Out is Low, and MP1 and p1 are "pull-up" transistors, so when A and B are both 'low', Out is pulled 'high'. This is a NOR gate, as I suspected. By the way, if p1 is the same kind of device as MP1 then they should be in the same orientation; one of them looks to be upside-down (not sure which, since I don't "know" this symbol)... Regards, Lawrence.

  • Both are the same devices. I think the second p1 is upside down as far as I noticed because I have to give the input to vdd so I rotated it. I didn't notice that this makes a huge difference. If the gate is directly connected to vdd, there is no need to connect gate to source? That is my question. If we could see both MP1 and MN0,MN1 gate is connected to source in case of pmos, gate is connected to ground in case of NMOS. So My question is, In case of p1, is there no need to connect gate to source?

    Regards

    Leo

  • Leo,

    What you are calling the "gate" is, in fact, the Bulk or Body connection, which is quite different from the gate. Hence in my first post I said that I think you are getting things confused...

    Regards,

    Lawrence.

  • None of the gates of the transistors are connected to vdd or gnd in this picture, so I have no idea what you're on about. The fact that one of the transistors is "upside down" shouldn't matter, because most of the time MOS devices are symmetrical - the source and drain are interchangeable.

    I'm wondering if you're just using strange terminology (which suggests you need to spend time learning about CMOS design if this is the case). I think you may be using the term "gate" to mean the device (or maybe even the bulk pin of the transistors?), and "source" to mean the vdd tap? Even then it doesn't make sense.

    If you're asking whether connecting the bulk pin directly to the tap (vdd or gnd) or wiring it to the MOSFET source, which is then connected to the tap (vdd or gnd), then it doesn't matter at all.

    Andrew.

  • I mean for me gate is bulk. Generally bulk is connected either to source or drain. In this case of p1, is it not needed to connect to source?

    Thank you for your help

    Regards

    Leo

  • If you call the bulk pin a "gate", then the world will be confused. So don't do that!

    Finally now that you're using the correct terminology, your question makes more sense.

    When you say that "generally bulk is connected to source or drain", that is not true. I'd say in most cases, the bulk is connected to either VDD (for PMOS) or VSS (for NMOS), certainly for logic circuits. For analog circuitry you sometimes have the bulk not at the supply potential (although that would only be when there is a well, and there is some benefit in doing this).

    Usually you want to ensure that the bulk potential is at least as high (for a PMOS) than all the pins so that nothing gets forward biassed.

    Regards,

    Andrew.

  • Sorry for the mistake. Generally bulk or body connection is connected either to source or ground. For MP1, bulk is connected to source or vdd. For MN0 and MN1, bulk is connected to ground or drain.

    In order to reduce body effect, we do this. In my case p1, is there no need to connect bulk and vdd?

    Thanks

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