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Connections between Bulk or gate and source for a PMOS

Leof

Hi,

I am new to cadence. I have a doubt. generally in PMOS gate is connected to source. IN my case gate is connected directly to vdd, and the other side of gate is connected to the output. In other words, I do not have free pin  to connect to the source. We connect it to reduce body effect. I came to know that we connect to ground in this case.

I am here by sending the schematic. Could you let me know how do I connect to the source for the second transistor p1

Thank you

Regards

Leo

Parents

  • Both are the same devices. I think the second p1 is upside down as far as I noticed because I have to give the input to vdd so I rotated it. I didn't notice that this makes a huge difference. If the gate is directly connected to vdd, there is no need to connect gate to source? That is my question. If we could see both MP1 and MN0,MN1 gate is connected to source in case of pmos, gate is connected to ground in case of NMOS. So My question is, In case of p1, is there no need to connect gate to source?

    Regards

    Leo

Reply

  • Both are the same devices. I think the second p1 is upside down as far as I noticed because I have to give the input to vdd so I rotated it. I didn't notice that this makes a huge difference. If the gate is directly connected to vdd, there is no need to connect gate to source? That is my question. If we could see both MP1 and MN0,MN1 gate is connected to source in case of pmos, gate is connected to ground in case of NMOS. So My question is, In case of p1, is there no need to connect gate to source?

    Regards

    Leo

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