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Connections between Bulk or gate and source for a PMOS

Leof

Hi,

I am new to cadence. I have a doubt. generally in PMOS gate is connected to source. IN my case gate is connected directly to vdd, and the other side of gate is connected to the output. In other words, I do not have free pin  to connect to the source. We connect it to reduce body effect. I came to know that we connect to ground in this case.

I am here by sending the schematic. Could you let me know how do I connect to the source for the second transistor p1

Thank you

Regards

Leo

Parents

  • If you call the bulk pin a "gate", then the world will be confused. So don't do that!

    Finally now that you're using the correct terminology, your question makes more sense.

    When you say that "generally bulk is connected to source or drain", that is not true. I'd say in most cases, the bulk is connected to either VDD (for PMOS) or VSS (for NMOS), certainly for logic circuits. For analog circuitry you sometimes have the bulk not at the supply potential (although that would only be when there is a well, and there is some benefit in doing this).

    Usually you want to ensure that the bulk potential is at least as high (for a PMOS) than all the pins so that nothing gets forward biassed.

    Regards,

    Andrew.

Reply

  • If you call the bulk pin a "gate", then the world will be confused. So don't do that!

    Finally now that you're using the correct terminology, your question makes more sense.

    When you say that "generally bulk is connected to source or drain", that is not true. I'd say in most cases, the bulk is connected to either VDD (for PMOS) or VSS (for NMOS), certainly for logic circuits. For analog circuitry you sometimes have the bulk not at the supply potential (although that would only be when there is a well, and there is some benefit in doing this).

    Usually you want to ensure that the bulk potential is at least as high (for a PMOS) than all the pins so that nothing gets forward biassed.

    Regards,

    Andrew.

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