failed to simulate veriloga in hspice : call to epvaHDLcgen failed

Hi all,

   
I'm trying to simulate a veriloga vccs in hspice.

Here is my veriloga code for vccs:

/ VerilogA for fishy1, asl6, veriloga

`include "constants.vams"
`include "disciplines.vams"

module asl6 (p, n, ps, ns);

inout p, n, ps, ns;
electrical p, n, ps, ns;
parameter g = 1.0;

analog begin

I(p, n) <+ g * V(ps, ns);

end

endmodule

And here is the netlist:

** Generated for: hspiceD
** Generated on: Mar  6 00:53:38 2015
** Design library name: fishy1
** Design cell name: asl7
** Design view name: schematic

.hdl "/home/somnathchakr/vlsix/veriloga.va"
.vec 'vector.vec'
.include "/opt/cadence/FreePDK45/FreePDK45/ncsu_basekit/models/hspice/hspice_nom.include"


.TEMP 25.0
.OPTION
+    ARTIST=2
+    INGOLD=2
+    PARHIER=LOCAL
+    PSF=2
+    POST=1

** Library name: fishy1
** Cell name: asl7
** View name: schematic
xi0 net5 b a 0 asl6 g=1
r0 net5 b 1

.tran 1p 10n

.END

And it gives me errors like this:

libepva built by pvamgr synmake_pva_build  on Sun May 22 07:53:10 PDT 2011
HSP_HOME:   /usr/synopsys/hspice/hspice
HSP_ARCH:   linux
HSP_GCC :   /usr/synopsys/hspice/hspice/GNU/amd64/gcc-4.2.2-static/bin/gcc
HSP_GCC_VER:
Working-Dir: /home/somnathchakr/vlsix
Args:        -p hsp -t spi -f Ictest5.pvadir/pvaHDL.lis -o Ictest5.pvadir


Begin of pVA compiling on Thu Mar 12 10:28:48 2015

Parsing '/home/somnathchakr/vlsix/veriloga.va'
Parsing include file '/usr/synopsys/hspice/hspice/include/constants.vams'
Parsing include file '/usr/synopsys/hspice/hspice/include/disciplines.vams'

End of pVA compiling on Thu Mar 12 10:28:48 2015


End of build pVA DB on Thu Mar 12 10:28:48 2015

*pvaI* Module (asl6): 4 unexpanded port, 0 init, 1 behav, 1 contrib, 12/0 expr(s)
*pvaI*              0 afCount, 0 fixDIS
*pvaI* Module (asl6): generated 0 flow node(s) during compilation.

End of pVA genC on Thu Mar 12 10:28:48 2015

*pvaI* #### Total 119 line-size(s), 12 expr(s), 1 contr(s), 0 init(s), 1 behav(s), 4 port(s)

Generating Ictest5.pvadir/pvaRTL_linux.so


End of submitting pVA Ictest5.pvadir/pvaRTL.mak on Thu Mar 12 10:28:48 2015

*pvaI* system & gcc return code is 512
 **error** call to epvaHDLcgen failed.
  **error** (Ictest5.sp:23) Definition of model/subckt "asl6" is not found for the element "xi0". Please specify a defined model/subckt name.

 **warning** multiple output options specified, using post


          ***** job aborted

Parsing '/home/somnathchakr/vlsix/veriloga.va' This means it can find my .va file, and read 'constants.vams' and 'disciplines.vams' in, but the error  Definition of model/subckt "asl6" is not found for the element "xi0" means it cannot find my defined circuit?

I googled the error "call to epvaHDLcgen failed.", people said it occurs because of the directory. But my directory is correct...I mean "/home/somnathchakr/vlsix/veriloga.va" is correct. Also, I tried to delete the ".hdl" line in the netlist file and add a command line " -hdl veriloga.va " in the command. It shows me the same error.

Could anyone help me with this? Thanks in advance!

Zongya