simInfo missing. Netlisting problem

If you normally use auCdl or auLvs, you still need to provide the simInfo for a leaf cell. This doesn't mean you're going to simulate it - the simInfo is just the part of the CDF which tells it how to netlist for a particular netlister - it's often for simulation, but not always.

Typically you need to create a stopping view, usually with the same name as the netlister (i.e. auCdl or auLvs) which is often just a copy of the symbol. Then set up the CDF for that component and in the auCdl or auLvs simInfo define the netlist procedure and terminal list. You may be able to do this by opening the symbol view and calling this SKILL function:

artGenerateHierSymbolCDF(geGetEditCellView())

(I think I got the case of the function correct - I don't have the documentation to hand). That will at least give you a good start.

Hope that helps.

Regards,

Andrew.

Hi Andrew,

Cheers,

Running artGenerateHierSymbolCDF(geGetEditCellView()) seems to have sorted the simInfo issue, however, a new problem has arisen.

I get this error now, ERROR (NVN-13010): Cell CCDgate is not defined.

CCDgate is the cell I created (added to the ruledeck etc.). This is just ruinning an LVS a simple layout containing only 4 of the CCDgate cells. If I chose auCdl it still passes LVS, but CreateCdl (which I require for LVSing the whole chip gives this error).

I'm not sure where it isn't defined? I'm pretty confident the ruledeck is as it should be, I have stopping cells, and now the CDF (simInfo) stuff seems to be resolved (I think).

If I export CDL on the schematic I'm using for the LVS It succeeds and I get a netlist. I guess it's using the other netlister. Any ideas?

Cheers,

Nick

Nick,

PVS is not my main area of expertise (I think you're using PVS?), but I'd check in the documentation for information on black box LVS. That's probably what you need.

I'm a bit short of time this week to do a detailed investigation - if you get stuck, contact customer support and then you can talk to one of our physical verification experts (I know a lot about physical verification in general, but don't spend time on PVS day to day so would have to do some research to find the answer, and I have the day job to do ;-> )

Regards,

Andrew.

No worries, cheers anyway.
I work for a University so can't contact customer support. We have some level of support, please don't email them on my behalf.
Do you know if there is a list of error codes available, I keep getting errors with codes reported, but as far as I can see there is no list stating what these mean, just the few words of text after the code which doesn't give much away. Such as the one I'm trying to decipher now, it doesn't even indicate whether the error is due to netlisting the schematic or layout. I've looked at the netlisting of both successful LVS's and unsuccessful (using the auCdl and CreateCdl) and the netlists appear to be identical in both cases.
Surely the whole point of error codes is so you can look them up to find out what they're trying to tell you.

Cheers anyway.

Nick

Nick,

Apologies - I could have done a bit of searching - and there's a solution based on this error:

I suspect you can't access that, but essentially the idea is that you need an empty .SUBCKT definition in the CDL netlist for the missing block.

Perhaps you can try that by hand by specifying an Include File on the File->Export->CDL form, and write the .SUBCKT in that include file. I think you can get auCdl to create this for you, but let's see whether it works first...

Andrew.

Hi Andrew,

Cheers. No I can't access that.

I'm not 100% sure what you're meaning by an include file. 

My cdl netlist appears to already have an empty .subckt in it for the CCDgate. This is the entire .CDL listing (bar the created/completed comments at the beginning and end of the file. The cell I created is CCDgate, and it's instantiated 4 times in the CCD_pixel_9 schematic/layout.

*pvsViewList = auCdl schematic
*pvsStopList = ("auCdl")
*pvsSimName = auCdl

*.EXPAND_ON_M_FACTOR

.subckt CCDgate cx
*PVSCELL netlisted from OU_EMCCD CCDgate auCdl
*.generic yes
.ends CCDgate

.subckt CCD_pixel_9 p1 p2 p3 p4
*PVSCELL netlisted from OU_EMCCD CCD_pixel_9 schematic
XI0 p1 CCDgate
XI1 p2 CCDgate
XI2 p3 CCDgate
XI3 p4 CCDgate
.ends CCD_pixel_9

I've created a netlist with the file->extract->cdl and the subck doesn't appear to be in that. Is this where the problem lies? I'm a bit confused about your include file instruction. 

************************************************************************
* auCdl Netlist:
*
* Library Name: OU_EMCCD
* Top Cell Name: CCD_pixel_9
* View Name: schematic
* Netlisted on: Mar 17 13:10:33 2015
************************************************************************

*.BIPOLAR
*.RESI = 2000
*.RESVAL
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM

************************************************************************
* Library Name: OU_EMCCD
* Cell Name: CCD_pixel_9
* View Name: schematic
************************************************************************

.SUBCKT CCD_pixel_9 p1 p2 p3 p4
*.PININFO p1:I p2:I p3:I p4:I
XI3 p4 / CCDgate
XI2 p3 / CCDgate
XI1 p2 / CCDgate
XI0 p1 / CCDgate
.ENDS

OK, I've found the include file option. I didn't see the scroll bar. And I see the issue with the .CDL file now. The one I looked at was created when I ran LVS with the auCDL option, but when I run it with the CreateCdl option it creates one without the subckt. So I need to get LVS with the creatCdl option to include a file with the empty subckt.

OK. I created a file with this in it (I called the file subckt.ckt although I doubt the name is important).

.subckt CCDgate cx
*PVSCELL netlisted from OU_EMCCD CCDgate auCdl
*.generic yes
.ends CCDgate

included this file in the CDL form, but the netlist it produced doesn't  have the subckt in it. 

Is this what you were asking me to do?

It should have a line near the top saying:

INCLUDE subckt.ckt

Rather than the contents being pasted into the netlist...

Regards,

Andrew.