Different scaling for MOS devices and Path/drawings after CDB to OA conversion

My guess is that there is a difference between the PDK versions you're using - maybe there's a migration script to move from one to the other? Perhaps you can check with the foundry.

Is there a good reason why you're doing this migration and using an old, unsupported version of IC61? We've had IC614, IC615 and IC616 since then, and only IC616 is currently supported (by supported I mean that we will generate fixes for production halting bugs). It seems an odd choice to migrate your design from CDB to OA but stick with such an old version.

Regards,

Andrew.

Hi Andrew,

Thank you for your reply.

I have tried the translation using a more recent version IC 6.1.5-64b.500.1. The problem remains.

The pdk revisions are the same in both CDB and OA.

The way I did the conversion is to install the PDK for OA and converted only the design library.

I did see a similar thread on this forum.

http://community.cadence.com/cadence_technology_forums/f/38/t/26109

In the above case, the problem was resolved using latest OA techlib. For my case, I am already using latest tsmcN65 techlib for OA.

Best regards,

Siladitya

Siladitya,

I would suggest you contact customer support about this so we can look at the data. It sounds highly likely it's PDK-related, but best if we can take a look. Or you should contact the foundry, in case they have any special migration scripts that you need to run.

Even then, you might want to use something newer than IC615 ISR1 (which is almost 4 years old).

Regards,

Andrew.

Dear Andrew,

I found out the root cause for the layout differences in CDB and OA.

In CDB the transistors have  DFM_options set to DFM+Analog.

When translated to OA and opened in IC6, the transistors shows DFM options set to minRule for both sch and lay. This leads to shrinking of transistors and thus apparent shift in layout.

Is there any switch in cadence that will set the default DFM_options to DFM+Analog ?

If you have any input on this, please let me know.

Thanks for your support,

Siladitya

This is a PDK-specific default, and the difference is presumably different to a change in default value between the CDB and OA version of the PDK.

Changing the default value in the CDF is unlikely to be enough, because if it doesn't match the pcell default, then you'll still have problems.

Most likely you'd need to have some SKILL code to go over every instance and change the DFM options property. I cannot imagine you are the first to have this issue, so carefully check the PDK documentation to see if the foundry already provides such a utility, or if not, you should contact them. If you have no joy with that, please contact Cadence customer support where we should be able to assist you.

Regards,

Andrew.

The "TSMC PDK tool" in virtuoso has an option "switch DFM options". I had to change the default DFM option of the entire TSMC65 pdk(OA version) library to "DFM+Analog" and it resolved the issue.

Thanks

Siladitya