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Different scaling for MOS devices and Path/drawings after CDB to OA conversion

Siladitya

Hi all,

I am using TSMC65 (CNM65GP). I converted a design from CDB to OA using CDB to OA translator GUI provided by cadence.

virtuoso version is 6.1.3.

In the translated layout, I see the drawn paths/recs are shifted for some reason. It might be due to different scaling factors for the MOS and drawings. Any help on how to resolve this issue is greatly appreciated.

An example snapshot is attached.

Thanks in advance,

Siladitya


Parents

  • This is a PDK-specific default, and the difference is presumably different to a change in default value between the CDB and OA version of the PDK.

    Changing the default value in the CDF is unlikely to be enough, because if it doesn't match the pcell default, then you'll still have problems.

    Most likely you'd need to have some SKILL code to go over every instance and change the DFM options property. I cannot imagine you are the first to have this issue, so carefully check the PDK documentation to see if the foundry already provides such a utility, or if not, you should contact them. If you have no joy with that, please contact Cadence customer support where we should be able to assist you.

    Regards,

    Andrew.

Reply

  • This is a PDK-specific default, and the difference is presumably different to a change in default value between the CDB and OA version of the PDK.

    Changing the default value in the CDF is unlikely to be enough, because if it doesn't match the pcell default, then you'll still have problems.

    Most likely you'd need to have some SKILL code to go over every instance and change the DFM options property. I cannot imagine you are the first to have this issue, so carefully check the PDK documentation to see if the foundry already provides such a utility, or if not, you should contact them. If you have no joy with that, please contact Cadence customer support where we should be able to assist you.

    Regards,

    Andrew.

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