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Layout XL: power router pt. 2

PNadeau

This is a second problem I have been having in the power router.  Has anyone encountered this before?

I'm trying to use the "Cell Rows" mode. I have placed some custom standard cells, set them as STDCELL in Edit -> Component Types, chosen a boundary and selected the GND net in the Navigator.

When I click run I get the following error: 

*WARNING*  No pins found on layer M1 for net GND.

The standard cells all have M1 pins on the ground and supply straps ("pin" purpose for both the pin and label).  I've also tried using the "drawing" purpose for the pin and "pin" purpose for the label, or both as "drawing" purpose, with no luck.

Perhaps I am using the tool incorrectly: If my cells are all exactly abutted, then the power and ground rows are connected across the cells already (power and ground straps built into the cell).  Ultimately I'm most interested in getting the "Via" mode of the power routing tool to route the vias from my power stripes (generated in the "Stripe" mode of the tool) down to the cell rows.  But the "Via" mode doesn't seem to recognize my custom cell rows because it is not inserting vias, hence why I tried the "Cell Rows" feature first, thinking it might only recognize rows generated by the tool....

IC 6.1.6.101, RHEL 6

Thanks in advance,

Phil

Parents

  • Dear Colin,

    Thanks for the quick response and workaround.  I understand this is probably a techfile issue.

    I did just try using the rtePowerRouteCellRow command in the CIW (following similar advice you gave in the other thread re: block ring insertion), and received a new message that did not appear when I was using the GUI.  Maybe this is a clue?

    *WARNING* This design has no defined rows for standard cells

    Afterwards I still get all of the "*WARNING* No pins found on layer M1 for net VSS" messages for all the layer and net combinations.

    For the workaround, could you point me to where I can use the digital placer to accomplish the stripe->rows->via tasks instead? I do have a small number of gates.  In the GUI I see "substrate" contacts, but I have those already.  I'm really hoping to find a way to have the tool(s) insert vias between the power stripes and the standard cell rows automatically.

    Thanks again for your help in these pages.  As an academic user, I'm not sure I have a direct line of communication to Cadence support.

    Cheers,

    Phil

Reply

  • Dear Colin,

    Thanks for the quick response and workaround.  I understand this is probably a techfile issue.

    I did just try using the rtePowerRouteCellRow command in the CIW (following similar advice you gave in the other thread re: block ring insertion), and received a new message that did not appear when I was using the GUI.  Maybe this is a clue?

    *WARNING* This design has no defined rows for standard cells

    Afterwards I still get all of the "*WARNING* No pins found on layer M1 for net VSS" messages for all the layer and net combinations.

    For the workaround, could you point me to where I can use the digital placer to accomplish the stripe->rows->via tasks instead? I do have a small number of gates.  In the GUI I see "substrate" contacts, but I have those already.  I'm really hoping to find a way to have the tool(s) insert vias between the power stripes and the standard cell rows automatically.

    Thanks again for your help in these pages.  As an academic user, I'm not sure I have a direct line of communication to Cadence support.

    Cheers,

    Phil

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