Layout XL: power router pt. 2

Hi Phil,

I answered another question of yours on another thread.

If the tech file is not setup correctly it may be the case of this problem as well.

It is difficult without seeing data.

Also, if the number of standard cells are not too large (less than a few thousand) then you may be able to use the Custom Digital Placer to do what you want. (row definition/power stripe generation and cell placement) followed by auto contact generation.

But to really solve this it may be necessary to contact customer support

Colin

Dear Colin,

Thanks for the quick response and workaround.  I understand this is probably a techfile issue.

I did just try using the rtePowerRouteCellRow command in the CIW (following similar advice you gave in the other thread re: block ring insertion), and received a new message that did not appear when I was using the GUI.  Maybe this is a clue?

*WARNING* This design has no defined rows for standard cells

Afterwards I still get all of the "*WARNING* No pins found on layer M1 for net VSS" messages for all the layer and net combinations.

For the workaround, could you point me to where I can use the digital placer to accomplish the stripe->rows->via tasks instead? I do have a small number of gates.  In the GUI I see "substrate" contacts, but I have those already.  I'm really hoping to find a way to have the tool(s) insert vias between the power stripes and the standard cell rows automatically.

Thanks again for your help in these pages.  As an academic user, I'm not sure I have a direct line of communication to Cadence support.

Cheers,

Phil

Hi Phil,

it may be because you are using layout views.

If you have used the abtract generator to generate correct abstract views you should not see the "no pins" message.

If you are using layouts then you will need to extract.

Now, I am not sure if the standard Virtuoso-XL extractor will be enough for the power router. So try this first.

 If not, you may need to open the stand-alone GUI (RIDE) and enter these commands:

Click "Launch" ->Virtuoso Routing Development Environment.

In the new window, enter:

extract_net_connectivity -all
proute_cell_row -nets {VSS! VDD!} -pin_layers Metal1 -row_end -power_only false   (for example)

You may also need to run rteCreateCellRowsScheme (in Virtuoso), before running this command.

Regarding the digital placer:

I hope your PDK is setup to use this (probably not) but here are a few key things you need to do.

If the standard cells are not identified by the placer you need to click Edit->component types

If you see no component types defined, it means the PDK has not set it up.

R.M.B Add component type. Give it any name you want (eg "my_stdcells")

Select the cells that you know are standard cells and click  RMB "move cells" and move them to the standard cells category

Click on your standard cell category and, at the bottom, define a component class of STDCELL. Then save everything

and go back to the Virtuoso Window.

Click place->custom digital->placement planning.

Play around with the rows and rails tabs and click the "Calculate Rows" button.

Check the CIW for any errors, correct, and try again. At the end you should see rows generated after clicking the calculate rows button.

You then run the placer with the place->custom digital->placer command.

Hopefully that's enough to get you started.

Colin

Dear Colin,

Thanks for the further information.  I tried both of these methods.

1) First, using the layout and the routing IDE with the suggested commands

extract_net_connectivity -all

proute_cell_row -nets {VSS! VDD!} -pin_layers Metal1 -row_end -power_only false

and also using the rteCreateCellRowsScheme to Virtuoso CIW beforehand (with appropriate parameters). Still the same warnings and no rows are routed.

Routing standard-cell rows ...
This design has no defined rows for standard cells.
Begin routing net GND standard-cell pins ...
No pins found on layer M1 for net GND
Begin routing net VDD standard-cell pins ...
No pins found on layer M1 for net VDD

2) Then, as suggested, I tried using abstract views instead of layout views.  I generated the abstracts from the layouts using the Cadence 'abstract' utility. This seems to get much closer.  I can route the block ring, stripes, and standard cell rows now.  The only thing not working is via insertion between the stripes and the standard cell rows.  I receive the following error:

Inserting vias between cell-rows and stripes ...
Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (1.7600, 8.8000)
Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (21.7600, 8.8000)
Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (26.7600, 8.8000)
Via failures from obstacles: 3.

The obstacles it is complaining about are in fact the VDD standard cell row nets that are iside the abstract views. It does seem to be able to create vias to any row metal outside of the abstract views that is created by the tool, but does not like the metal inside the abstract view.  Unfortunately most of the row metal (M1) is already inside my standard cell (since the straps are inside the cells).  So if the cells are abutted, and this metal is considered an obstacle then there is no place for the tool to place the vias.  I wonder if there is a solution to this as well.

Quite a marathon to get this working. But if I can get this flow down, then laying out 1000's of custom cells should be a breeze!

Thanks again for your help in the forums.

Best,
Phil

Hi Phil,

it's getting a bit more difficult now without looking at data.

If I understand correctly, GND was O.K but not VDD?

Either the connectivity was not extracted correctly or it is not possible to place the via because of design rule violations.

One check for connectivity:

Use the Dynamic Select Assistant and move your mouse over the standard cell power/ground shapes.

You should see net names displayed along with other info for the shapes under the cursor. If you do not see VDD then this may be the problem.

You may also see a metal blockage, rather than a drawing shape with connectivity. This is a sign that the abstract generator has not extracted the connectivity correctly.

Perhaps there is not enough room to place the vias? Perhaps you have the wrong via defined in your constraint group for the router?

Try placing the via manually where you think it should be correct.

Then run the DRD batch checker (verify->design with "process rules" selected.)

If you see any errors then that will be the reason for the failed via generation.

You then need to find out if it is a real error or maybe a PDK techlib error (quite common)

Regards

Colin