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Layout XL: power router pt. 2

PNadeau

This is a second problem I have been having in the power router.  Has anyone encountered this before?

I'm trying to use the "Cell Rows" mode. I have placed some custom standard cells, set them as STDCELL in Edit -> Component Types, chosen a boundary and selected the GND net in the Navigator.

When I click run I get the following error: 

*WARNING*  No pins found on layer M1 for net GND.

The standard cells all have M1 pins on the ground and supply straps ("pin" purpose for both the pin and label).  I've also tried using the "drawing" purpose for the pin and "pin" purpose for the label, or both as "drawing" purpose, with no luck.

Perhaps I am using the tool incorrectly: If my cells are all exactly abutted, then the power and ground rows are connected across the cells already (power and ground straps built into the cell).  Ultimately I'm most interested in getting the "Via" mode of the power routing tool to route the vias from my power stripes (generated in the "Stripe" mode of the tool) down to the cell rows.  But the "Via" mode doesn't seem to recognize my custom cell rows because it is not inserting vias, hence why I tried the "Cell Rows" feature first, thinking it might only recognize rows generated by the tool....

IC 6.1.6.101, RHEL 6

Thanks in advance,

Phil

Parents

  • Hi Phil,

    it's getting a bit more difficult now without looking at data.

    If I understand correctly, GND was O.K but not VDD?

    Either the connectivity was not extracted correctly or it is not possible to place the via because of design rule violations.

    One check for connectivity:

    Use the Dynamic Select Assistant and move your mouse over the standard cell power/ground shapes.

    You should see net names displayed along with other info for the shapes under the cursor. If you do not see VDD then this may be the problem.

    You may also see a metal blockage, rather than a drawing shape with connectivity. This is a sign that the abstract generator has not extracted the connectivity correctly.

    Perhaps there is not enough room to place the vias? Perhaps you have the wrong via defined in your constraint group for the router?

    Try placing the via manually where you think it should be correct.

    Then run the DRD batch checker (verify->design with "process rules" selected.)

    If you see any errors then that will be the reason for the failed via generation.

    You then need to find out if it is a real error or maybe a PDK techlib error (quite common)

    Regards

     

    Colin

Reply

  • Hi Phil,

    it's getting a bit more difficult now without looking at data.

    If I understand correctly, GND was O.K but not VDD?

    Either the connectivity was not extracted correctly or it is not possible to place the via because of design rule violations.

    One check for connectivity:

    Use the Dynamic Select Assistant and move your mouse over the standard cell power/ground shapes.

    You should see net names displayed along with other info for the shapes under the cursor. If you do not see VDD then this may be the problem.

    You may also see a metal blockage, rather than a drawing shape with connectivity. This is a sign that the abstract generator has not extracted the connectivity correctly.

    Perhaps there is not enough room to place the vias? Perhaps you have the wrong via defined in your constraint group for the router?

    Try placing the via manually where you think it should be correct.

    Then run the DRD batch checker (verify->design with "process rules" selected.)

    If you see any errors then that will be the reason for the failed via generation.

    You then need to find out if it is a real error or maybe a PDK techlib error (quite common)

    Regards

     

    Colin

Children
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