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Layout XL: power router pt. 2

PNadeau

This is a second problem I have been having in the power router.  Has anyone encountered this before?

I'm trying to use the "Cell Rows" mode. I have placed some custom standard cells, set them as STDCELL in Edit -> Component Types, chosen a boundary and selected the GND net in the Navigator.

When I click run I get the following error: 

*WARNING*  No pins found on layer M1 for net GND.

The standard cells all have M1 pins on the ground and supply straps ("pin" purpose for both the pin and label).  I've also tried using the "drawing" purpose for the pin and "pin" purpose for the label, or both as "drawing" purpose, with no luck.

Perhaps I am using the tool incorrectly: If my cells are all exactly abutted, then the power and ground rows are connected across the cells already (power and ground straps built into the cell).  Ultimately I'm most interested in getting the "Via" mode of the power routing tool to route the vias from my power stripes (generated in the "Stripe" mode of the tool) down to the cell rows.  But the "Via" mode doesn't seem to recognize my custom cell rows because it is not inserting vias, hence why I tried the "Cell Rows" feature first, thinking it might only recognize rows generated by the tool....

IC 6.1.6.101, RHEL 6

Thanks in advance,

Phil

Parents

  • Dear Colin,

    Thanks for the further information.  I tried both of these methods.

    1) First, using the layout and the routing IDE with the suggested commands

    extract_net_connectivity -all

    proute_cell_row -nets {VSS! VDD!} -pin_layers Metal1 -row_end -power_only false

    and also using the rteCreateCellRowsScheme to Virtuoso CIW beforehand (with appropriate parameters). Still the same warnings and no rows are routed.

    Routing standard-cell rows ...
    This design has no defined rows for standard cells.
    Begin routing net GND standard-cell pins ...
    No pins found on layer M1 for net GND
    Begin routing net VDD standard-cell pins ...
    No pins found on layer M1 for net VDD

    2) Then, as suggested, I tried using abstract views instead of layout views.  I generated the abstracts from the layouts using the Cadence 'abstract' utility. This seems to get much closer.  I can route the block ring, stripes, and standard cell rows now.  The only thing not working is via insertion between the stripes and the standard cell rows.  I receive the following error:

    Inserting vias between cell-rows and stripes ...
    Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (1.7600, 8.8000)
    Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (21.7600, 8.8000)
    Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (26.7600, 8.8000)
    Via failures from obstacles: 3.

    The obstacles it is complaining about are in fact the VDD standard cell row nets that are iside the abstract views. It does seem to be able to create vias to any row metal outside of the abstract views that is created by the tool, but does not like the metal inside the abstract view.  Unfortunately most of the row metal (M1) is already inside my standard cell (since the straps are inside the cells).  So if the cells are abutted, and this metal is considered an obstacle then there is no place for the tool to place the vias.  I wonder if there is a solution to this as well.

    Quite a marathon to get this working. But if I can get this flow down, then laying out 1000's of custom cells should be a breeze!

    Thanks again for your help in the forums.

    Best,
    Phil

Reply

  • Dear Colin,

    Thanks for the further information.  I tried both of these methods.

    1) First, using the layout and the routing IDE with the suggested commands

    extract_net_connectivity -all

    proute_cell_row -nets {VSS! VDD!} -pin_layers Metal1 -row_end -power_only false

    and also using the rteCreateCellRowsScheme to Virtuoso CIW beforehand (with appropriate parameters). Still the same warnings and no rows are routed.

    Routing standard-cell rows ...
    This design has no defined rows for standard cells.
    Begin routing net GND standard-cell pins ...
    No pins found on layer M1 for net GND
    Begin routing net VDD standard-cell pins ...
    No pins found on layer M1 for net VDD

    2) Then, as suggested, I tried using abstract views instead of layout views.  I generated the abstracts from the layouts using the Cadence 'abstract' utility. This seems to get much closer.  I can route the block ring, stripes, and standard cell rows now.  The only thing not working is via insertion between the stripes and the standard cell rows.  I receive the following error:

    Inserting vias between cell-rows and stripes ...
    Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (1.7600, 8.8000)
    Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (21.7600, 8.8000)
    Failed net VDD, encountered obstacle for prospective via on layer VIA1 centered at (26.7600, 8.8000)
    Via failures from obstacles: 3.

    The obstacles it is complaining about are in fact the VDD standard cell row nets that are iside the abstract views. It does seem to be able to create vias to any row metal outside of the abstract views that is created by the tool, but does not like the metal inside the abstract view.  Unfortunately most of the row metal (M1) is already inside my standard cell (since the straps are inside the cells).  So if the cells are abutted, and this metal is considered an obstacle then there is no place for the tool to place the vias.  I wonder if there is a solution to this as well.

    Quite a marathon to get this working. But if I can get this flow down, then laying out 1000's of custom cells should be a breeze!

    Thanks again for your help in the forums.

    Best,
    Phil

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