Stats

Locked Locked
Replies 4
Subscribers 126
Views 22476
Members are here 0

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Failed to build VDB. Cannot submit DRC Run

V4vlsi over 10 years ago

Hi,

while doing simple DRC Run of an simple inverter Layout. I am getting the following error.

Loading tech rule set file : /mnt/Newhdd/Cadence_tools/UMC180/RuleDecks/Assura/techRuleSets

Assura DRC: State saved "Last"

Loading tech rule set file : /mnt/Newhdd/Cadence_tools/UMC180/RuleDecks/Assura/techRuleSets

Compiling rules...

*Error* load: can't access file - "/Newhdd/PDKS/UMC180/RuleDecks/Assura/DRC/G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul"

Errors exist in the rules file '/mnt/Newhdd/Cadence_tools/UMC180/RuleDecks/Assura/./DRC/G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.11-p1.rul'.

*WARNING* Failed to build VDB. Cannot submit DRC Run.

Assura DRC: State loaded "Last"

I am using Cadence Virtuoso version IC6.1.5.500.11. and DRC engine ASSURA 4.1_USR2HF2. Is there any compatibility issue thit the version of virtuoso and ASSURA.?

PLZ help. Thanks in advance.

Andrew Beckett over 10 years ago

I'm not sure why you think it's a compatibility issue? The error message looks pretty clear to me - something is referencing a file, and it can't find that file. Since the file in question appears to be part of the rule decks, it suggests a problem with the installation of the rule decks, not the tool.

Check to see if the path in question exists - maybe it is a permission problem? Then look at the other files to see where this is referenced - maybe there is a switch you need to set to avoid this. Also check whether it has been installed correctly. Finally, check with the providers of the rule decks...

Regards,

Andrew.
Cancel
Vote Up 0 Vote Down

Cancel
kapiljainwal over 9 years ago

Dear Andrew,

I am also facing the same error.

I am working on IC615. LVS is running fine but DRC is showing the error that "Failed to built VDB, Cannot submit the DRC run."

One more this I found that while I am opening the "Open Run" under "Assura" tab I can only see run name as LVS and not for DRC.

I am not able to resolve the problem. Is it due to missing run name file for DRC or something else because LVS is running properly.
Cancel
Vote Up 0 Vote Down

Cancel
Andrew Beckett over 9 years ago

If the problem is exactly the same (with the same preceding errors), then my guess is now as it was then, that you have a permission problem. However, you didn't show what all the errors were - only the final error (which is probably the consequence of an earlier error).

It's hardly surprising that the run name for the DRC is missing from the Open Run, because the run didn't complete - Open Run only shows you completed runs.

Regards,

Andrew.
Cancel
Vote Up 0 Vote Down

Cancel
kapiljainwal over 9 years ago

Dear Andrew,
I got the solution. The rule file (G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.9-p2.rul) contains the path of another rule file (G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul) which was located at different place then the mentioned path. I changed the path of later one and now DRC is working fine.

Thanks,
Kapil Jainwal
Cancel
Vote Up 0 Vote Down

Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.