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Basic Verilog-A Question

Teem

Hi,


    I am new to verilog-A. I wrote a simple verilog-A code and proceeded transient simulation in Cadence ADS. My code, transient simulation setting and results are as below. I cannot figure out why the output is incorrect. By the way, there is no warning or error during the simulation.

    Thank you for your kind advice.

Best regards,

1. Verilog-A code:

2. Testbench:

3. Transient simulation:

4. Incorrect output:

Parents

  • Nothing obvious - I just tried this and it worked fine for me (I'm not using IC5141, but I can't see why that would matter). I also just checked with IC5141 and it was OK.

    Can you use Simulation->Netlist->Display in ADE and then post the contents? (ideally as text, rather than posting a picture of the window - it's a bit hard to cut and paste from a picture, or search pictures).

    Regards,

    Andrew.

Reply

  • Nothing obvious - I just tried this and it worked fine for me (I'm not using IC5141, but I can't see why that would matter). I also just checked with IC5141 and it was OK.

    Can you use Simulation->Netlist->Display in ADE and then post the contents? (ideally as text, rather than posting a picture of the window - it's a bit hard to cut and paste from a picture, or search pictures).

    Regards,

    Andrew.

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