Basic Verilog-A Question

Nothing obvious - I just tried this and it worked fine for me (I'm not using IC5141, but I can't see why that would matter). I also just checked with IC5141 and it was OK.

Can you use Simulation->Netlist->Display in ADE and then post the contents? (ideally as text, rather than posting a picture of the window - it's a bit hard to cut and paste from a picture, or search pictures).

Regards,

Andrew.

The above shows what it looked like for me in wavescan.

I didn't run in ADE (that shouldn't matter, unless you've got some strange netlisting problem - which sharing your netlist should reveal), but instead used:

`include "disciplines.vams"

module testVlog(in,out);
input in;
output out;
voltage in,out;

analog begin
        V(out) <+ idt(V(in),0);
end
endmodule

and then this spectre netlist (hand written):

//
V0 (n1 0) vsource dc=1
I0 (n1 vout) testVlog

ahdl_include "testVlog.va"

tran tran stop=100

Regards,

Andrew.

Dear Andrew:

    Thank you very much for testing the code for me.

    I am sorry that I cannot post the netlist as text because our MIS people restricted the privilege from doing that. Below is the hardcopy of my netlist. I did not past the verilog-A code again because it's the same as what I posted in the beginning. I also post some key information from spectre.out that might help.

    Thanks a gain for your help.

Best regards,

1. Netlist:

2. Spectre.out

Nothing unusual there, apart from the ancient versions of the software you're using. I don't have access to IC5141 USR5 (I have USR6 from October 2008, and an older version, USR1 won't run at all). I did also try with MMSIM72.

With the versions I had, I ran and it all worked OK. The plot you gave only had a very short x-axis, so I'm wondering if this was a problem with the SST2 output format if you change the stop time massively between runs. What I'd suggest is closing everything (exiting icfb), deleting the simulation results directory to be sure, and then starting icfb again and entering:

envSetVal("spectre.envOpts" "simOutputFormat" 'string "psfbin")

before starting the Analog Design Environment window and running the simulation again. This may not be it, but I can't see anything else unusual - all looks OK to me.

Regards,

Andrew.

Dear Andrew:

So great, intruction you suggest works!

Thank you so much clarifying this issue for me.

Have a nice day :)

Best regards,