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Basic Verilog-A Question

Teem

Hi,


    I am new to verilog-A. I wrote a simple verilog-A code and proceeded transient simulation in Cadence ADS. My code, transient simulation setting and results are as below. I cannot figure out why the output is incorrect. By the way, there is no warning or error during the simulation.

    Thank you for your kind advice.

Best regards,

1. Verilog-A code:

2. Testbench:

3. Transient simulation:

4. Incorrect output:

Parents

  • Nothing unusual there, apart from the ancient versions of the software you're using. I don't have access to IC5141 USR5 (I have USR6 from October 2008, and an older version, USR1 won't run at all). I did also try with MMSIM72.

    With the versions I had, I ran and it all worked OK. The plot you gave only had a very short x-axis, so I'm wondering if this was a problem with the SST2 output format if you change the stop time massively between runs. What I'd suggest is closing everything (exiting icfb), deleting the simulation results directory to be sure, and then starting icfb again and entering:

    envSetVal("spectre.envOpts" "simOutputFormat" 'string "psfbin")

    before starting the Analog Design Environment window and running the simulation again. This may not be it, but I can't see anything else unusual - all looks OK to me.

    Regards,

    Andrew.

Reply

  • Nothing unusual there, apart from the ancient versions of the software you're using. I don't have access to IC5141 USR5 (I have USR6 from October 2008, and an older version, USR1 won't run at all). I did also try with MMSIM72.

    With the versions I had, I ran and it all worked OK. The plot you gave only had a very short x-axis, so I'm wondering if this was a problem with the SST2 output format if you change the stop time massively between runs. What I'd suggest is closing everything (exiting icfb), deleting the simulation results directory to be sure, and then starting icfb again and entering:

    envSetVal("spectre.envOpts" "simOutputFormat" 'string "psfbin")

    before starting the Analog Design Environment window and running the simulation again. This may not be it, but I can't see anything else unusual - all looks OK to me.

    Regards,

    Andrew.

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