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Basic Verilog-A Question

Teem

Hi,


    I am new to verilog-A. I wrote a simple verilog-A code and proceeded transient simulation in Cadence ADS. My code, transient simulation setting and results are as below. I cannot figure out why the output is incorrect. By the way, there is no warning or error during the simulation.

    Thank you for your kind advice.

Best regards,

1. Verilog-A code:

2. Testbench:

3. Transient simulation:

4. Incorrect output:

Parents

  • The above shows what it looked like for me in wavescan.

    I didn't run in ADE (that shouldn't matter, unless you've got some strange netlisting problem - which sharing your netlist should reveal), but instead used:

    `include "disciplines.vams"

    module testVlog(in,out);
    input in;
    output out;
    voltage in,out;

    analog begin
            V(out) <+ idt(V(in),0);
    end
    endmodule

    and then this spectre netlist (hand written):

    //
    V0 (n1 0) vsource dc=1
    I0 (n1 vout) testVlog

    ahdl_include "testVlog.va"

    tran tran stop=100

    Regards,

    Andrew.

Reply

  • The above shows what it looked like for me in wavescan.

    I didn't run in ADE (that shouldn't matter, unless you've got some strange netlisting problem - which sharing your netlist should reveal), but instead used:

    `include "disciplines.vams"

    module testVlog(in,out);
    input in;
    output out;
    voltage in,out;

    analog begin
            V(out) <+ idt(V(in),0);
    end
    endmodule

    and then this spectre netlist (hand written):

    //
    V0 (n1 0) vsource dc=1
    I0 (n1 vout) testVlog

    ahdl_include "testVlog.va"

    tran tran stop=100

    Regards,

    Andrew.

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