Stats

  • Locked Locked
  • Replies 5
  • Subscribers 126
  • Views 6040
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Assura DRC errors - UMC 90nm

GURU M

Hello,
 I designed an inverter and has drawn a layout. After checking for Assura DRC errors, I got these errors. Please help me in solving these errors and how to waive the errors in Cadence.

[1] 4.1.1G. a: Minimum diffusion density over 150umX150um area, stepping 50um is 25%.

[3] 4.2.1. 1C: Minimum spacing and notch of metal-1 regions is 0.12um.

[1] 4.2.1.DEN.1G.M1_LT20: The Metal1 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M2_LT20: The Metal2 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M3_LT20: The Metal3 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M4_LT20: The Metal4 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M5_LT20: The Metal5 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M6_LT20: The Metal6 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M7_LT20: The Metal7 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M8_LT20: The Metal8 coverage must be larger than 20% over local 100um * 100um area step 50um.

[1] 4.2.1.DEN.1G.M9_LT20: The Metal9 coverage must be larger than 20% over local 100um * 100um area step 50um.

[16] 5.1.DIFF: Die seal ring rule 1, diffusion must take a turn with 135-angle within regions 150um away from die corners.

[28] 5.1.ME1:Die seal ring rule 1, metal-1 must take a turn with 135-angle within regions 150um away from die corners.

[40] 6A.ME1_NSR: Die corner rule 1, ME1 must draw with 135 angle.

[2] 4.1.8AaBaC_DFM.Priority3: Minimum PO1 width for interconnect is 0.12um when PO1 to diffusion spacing > 0.2um

[28] 4.1.13C.a_DFM.Priority3: Minimum spacing of DIFF CONT to PO1 is 0.1um, PO1 with width < 0.13um

[4] 4.2.1.1D.b1b2_DFM.Priority4: Minimum ME1 line end enclosure of CONT at ME1 outer corner is 0.06um, Minimum ME1 line end enclosure of CONT for four sides is 0.02um, Minimum ME1 line end enclosure of CONT is 0.06um

[28] 4.1.13F_DFM.Priority5: Minimum extension of an DIFF region beyond a CONT region is 0.06um

[2] Design_guideline2: NWEL overlap PFET diffusion edge is recommended to be not less than 0.5um

  • Hi Guru

    I think the error messages are actually quite self-explanatory. E.g.

    a. Spacing error means that you have to increase the separate between 2 shapes

    b. The coverage error means that Assura checks the layout using 50x50um windows and found that the density of the layer in specific windows are insufficient. You need to add more of that layer in those windows.

    You can waive errors using avParameter ?exceptionFile. Please search for "Error Signoffs" in $ASSURAHOME/doc/assurauser/assurauser.pdf.

    Best regards
    Quek

  • Thank you Mr.Quek. I could get through those DRC errors. Now I am having trouble running LVS. Please help me solve this.

    *ERROR* Segmentation violation - run abnormally terminated

    *WARNING* Translation abnormally terminated!

    *WARNING* aveng exit with bad status
    *WARNING* Status 256
    *WARNING* Assura execution terminated



  • Hi Guru

    "Segmentation violation" simply means that Assura has crashed. You can check your current version of Assura using the following cmd:

    terminal>assura -W

    If you are not using the latest version of Assura, you should switch to the latest version and retry LVS. The crash might be due to a bug which might have already been fixed in the latest version.

    Best regards
    Quek

  • Hey Quek,
     I could resolve all the problems with DRC and LVS. And now I am facing the problem with RCX. After LVS, I clicked on Run RCX and a window popped up saying "No technology directory found". Please help me get through this.

  • Hi Guru

    Since we have already resolved the DRC errors, it would be good for you to start new issues in new threads that other users can understand the issues more easily.

    You will need a Quantus package from the foundry in order to do parasitic extraction. It is ok to ignore the "No technology directory found" warning. Technology setup is done using a file named "techRuleSets". The warning simply means that it cannot find this file. You can specify the path to the Quantus package in the "Setup" tab of the Quantus form.

    Best regards
    Quek

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.