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Schematic and layout with multiple power pins

naveiitb

Hi,

I am trying to design a chip which is going to have multiple power and gnd pins. These pins will be shorted in layout through the circuit, but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

Is there a way to make the schematic aware of this? I cant possibly define multiple names (VDD1, VDD2,.. etc ) on the same power net. Also the layout extractor does not allow multiple names on the same net.

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  • Dear naveiitb,

    >  but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

    I do not believe this is necessary. In all of my layouts, there are multilple power and ground pins dispersed through the supply and ground planes. However, they all have the same name and that name is the same as the supply and ground node net name on the schematic. It is often required to have multiple pins in the layout as, otherwise, all the supply current will flow through a single pin which will result in an artificially high resistive drop.

    Shawn

Reply

  • Dear naveiitb,

    >  but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

    I do not believe this is necessary. In all of my layouts, there are multilple power and ground pins dispersed through the supply and ground planes. However, they all have the same name and that name is the same as the supply and ground node net name on the schematic. It is often required to have multiple pins in the layout as, otherwise, all the supply current will flow through a single pin which will result in an artificially high resistive drop.

    Shawn

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