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  3. Schematic and layout with multiple power pins

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Schematic and layout with multiple power pins

naveiitb
naveiitb over 10 years ago

Hi,

I am trying to design a chip which is going to have multiple power and gnd pins. These pins will be shorted in layout through the circuit, but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

Is there a way to make the schematic aware of this? I cant possibly define multiple names (VDD1, VDD2,.. etc ) on the same power net. Also the layout extractor does not allow multiple names on the same net.

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  • ShawnLogan
    ShawnLogan over 10 years ago

    Dear naveiitb,

    >  but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

    I do not believe this is necessary. In all of my layouts, there are multilple power and ground pins dispersed through the supply and ground planes. However, they all have the same name and that name is the same as the supply and ground node net name on the schematic. It is often required to have multiple pins in the layout as, otherwise, all the supply current will flow through a single pin which will result in an artificially high resistive drop.

    Shawn

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  • naveiitb
    naveiitb over 10 years ago

    That is fine, and is what I too am following as of now. However depending on the positions of there various gnd and vdd pads, and pins to which they are connected, the package parasitics will be different.

    For example in a BGA package the different rings of pins have very different parasitics, in a QFN package the corner and center pins have different bond wire lengths etc. So I would want to put different package parasitic models on different pins and hence extract the layout of gnd and vdd planes with multiple labels. I hope my query is clear.

    Naveen

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  • ShawnLogan
    ShawnLogan over 10 years ago

    Dear Naveen,

    > However depending on the positions of there various gnd and vdd pads, and pins to which they are connected, the package parasitics will be different.

    I now understand your motivation. One possibility that I have used in similar situations is to define different nodes for each specific extracted view output pin (i.e., vdd_a, vdd_b, vdd_c...). Each node is connected to the global VDD plane through a metal resistor. Each resistor is a segment of the metal making up that particular segment leading to your VDD plane. For example, one metal resistor placed on the same level as your VDD plane extends to the corner pin, a second extends to a different corner. Schematically, your VDD connection is broken up into many different pins, but each pin will correspond to the specific node you want to connect the corresponding package model.

    I'm not knowledgeable enough to know of a different way to uniquely identify a particular layout location on an extracted view without defining a new pin for that location.

    Perhaps others have a better idea...

    Shawn

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  • naveiitb
    naveiitb over 10 years ago

    Dear Shawn,

    Actually I had used metal resistors in a design earlier. However the technology I am using right now does not have metal resistors in the PDK. I will try to see if I can make a resistor and add it to the PDK locally. In case you have done such a thing before can you point me to some tutorial or such? Or is it designkit dependent?

    Thank you

    Naveen

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