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Schematic and layout with multiple power pins

naveiitb

Hi,

I am trying to design a chip which is going to have multiple power and gnd pins. These pins will be shorted in layout through the circuit, but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

Is there a way to make the schematic aware of this? I cant possibly define multiple names (VDD1, VDD2,.. etc ) on the same power net. Also the layout extractor does not allow multiple names on the same net.

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  • Dear Naveen,

    > However depending on the positions of there various gnd and vdd pads, and pins to which they are connected, the package parasitics will be different.

    I now understand your motivation. One possibility that I have used in similar situations is to define different nodes for each specific extracted view output pin (i.e., vdd_a, vdd_b, vdd_c...). Each node is connected to the global VDD plane through a metal resistor. Each resistor is a segment of the metal making up that particular segment leading to your VDD plane. For example, one metal resistor placed on the same level as your VDD plane extends to the corner pin, a second extends to a different corner. Schematically, your VDD connection is broken up into many different pins, but each pin will correspond to the specific node you want to connect the corresponding package model.

    I'm not knowledgeable enough to know of a different way to uniquely identify a particular layout location on an extracted view without defining a new pin for that location.

    Perhaps others have a better idea...

    Shawn

Reply

  • Dear Naveen,

    > However depending on the positions of there various gnd and vdd pads, and pins to which they are connected, the package parasitics will be different.

    I now understand your motivation. One possibility that I have used in similar situations is to define different nodes for each specific extracted view output pin (i.e., vdd_a, vdd_b, vdd_c...). Each node is connected to the global VDD plane through a metal resistor. Each resistor is a segment of the metal making up that particular segment leading to your VDD plane. For example, one metal resistor placed on the same level as your VDD plane extends to the corner pin, a second extends to a different corner. Schematically, your VDD connection is broken up into many different pins, but each pin will correspond to the specific node you want to connect the corresponding package model.

    I'm not knowledgeable enough to know of a different way to uniquely identify a particular layout location on an extracted view without defining a new pin for that location.

    Perhaps others have a better idea...

    Shawn

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