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Schematic and layout with multiple power pins

naveiitb

Hi,

I am trying to design a chip which is going to have multiple power and gnd pins. These pins will be shorted in layout through the circuit, but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

Is there a way to make the schematic aware of this? I cant possibly define multiple names (VDD1, VDD2,.. etc ) on the same power net. Also the layout extractor does not allow multiple names on the same net.

Parents

  • Dear Shawn,

    Actually I had used metal resistors in a design earlier. However the technology I am using right now does not have metal resistors in the PDK. I will try to see if I can make a resistor and add it to the PDK locally. In case you have done such a thing before can you point me to some tutorial or such? Or is it designkit dependent?

    Thank you

    Naveen

Reply

  • Dear Shawn,

    Actually I had used metal resistors in a design earlier. However the technology I am using right now does not have metal resistors in the PDK. I will try to see if I can make a resistor and add it to the PDK locally. In case you have done such a thing before can you point me to some tutorial or such? Or is it designkit dependent?

    Thank you

    Naveen

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