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Schematic and layout with multiple power pins

naveiitb

Hi,

I am trying to design a chip which is going to have multiple power and gnd pins. These pins will be shorted in layout through the circuit, but I need to keep separate names for them in order to extract the layout and simulate the extracted netlist with the package parasitics. 

Is there a way to make the schematic aware of this? I cant possibly define multiple names (VDD1, VDD2,.. etc ) on the same power net. Also the layout extractor does not allow multiple names on the same net.

Parents

  • That is fine, and is what I too am following as of now. However depending on the positions of there various gnd and vdd pads, and pins to which they are connected, the package parasitics will be different.

    For example in a BGA package the different rings of pins have very different parasitics, in a QFN package the corner and center pins have different bond wire lengths etc. So I would want to put different package parasitic models on different pins and hence extract the layout of gnd and vdd planes with multiple labels. I hope my query is clear.

    Naveen

Reply

  • That is fine, and is what I too am following as of now. However depending on the positions of there various gnd and vdd pads, and pins to which they are connected, the package parasitics will be different.

    For example in a BGA package the different rings of pins have very different parasitics, in a QFN package the corner and center pins have different bond wire lengths etc. So I would want to put different package parasitic models on different pins and hence extract the layout of gnd and vdd planes with multiple labels. I hope my query is clear.

    Naveen

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