• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. ADE-L simulation problem

Stats

  • Locked Locked
  • Replies 5
  • Subscribers 125
  • Views 16527
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ADE-L simulation problem

gonsays1
gonsays1 over 10 years ago

Hello,

I've been designing a Two-stage CMOS OTA folded cascode amplifier and now I'm simulating the circuit, in order to get the values of certain parameters (slew-rate, small signal gain, bandwidth, phase margin and GBW product).

The first image is the simulation bench, the second image is the schematic of the Amplifier2 symbol and the third image are the properties of the MOS transistors.

First test:

I've started to simulate the circuit on ADE-L using adequated variables for the dimensions of each transistor (as an example: transistor M11 will have width strip and width defined as variable W11 and length as L11).

I've loaded all the variables to the ADE-L and gave them suitable values. On the output, I've used the calculator to get the functions of the referred parameters, getting the following results:

Av=70.85dB
SR=205.3M
Bw=67.47kHz
PM=62.51
GBW=235.9M

 

Second test:

After getting those results, I've replaced the variables on the transistor properties for exactly the same value used as the variable (as an example you can check the last image: for the transistor M5 on the ADE-L I had L5=0.55u and W5=13.5u - on that image you can see that I've changed L5 for 0.55u, for instance).

After replacing all the variables for their associated value on the simulation I got different values for the parameters (using the same dimensions):

Av=70.82dB
SR=201.5M
Bw=67.12k
PM=56.83
GBW=234M

Problem:


As you can see, it makes no sense using the same dimensions (with and without variables on the transistor properties) and getting different results.

Is there any way to get the "real" results? I mean, the same result for both cases?

The last image shows the properties of the transistors (on the 2nd test - with assigned values), is there any option that should be changed?

Thank you very much in advance! :)

Best Regards,

G

Simulation schematic:

Amplifier2 schematic:

 

Transistor properties (schematic):

  • Cancel
Parents
  • Tom Volden
    Tom Volden over 10 years ago

    Hi,

    The most likely cause of the differences in simulation results is that in the case where you are putting the fixed values in the schematics the callbacks associated with those parameter are being executed.  This means that secondary parameters such as source/drain diffusion areas and peripheries are updated when you change the length and width values.  When using design variables only the length or width value is changed by the parameter since they are inserted at simulation time and the simulator doesn't know about the PDK callbacks.

    So to answer your question, the "real" results are those from your second case where you have fixed values in your design.  You can also achieve these identical results if you use parameterization in ADE XL as this flow triggers the callbacks when updating parameter values prior to netlisting.

    Regards,

    TOM

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Tom Volden
    Tom Volden over 10 years ago

    Hi,

    The most likely cause of the differences in simulation results is that in the case where you are putting the fixed values in the schematics the callbacks associated with those parameter are being executed.  This means that secondary parameters such as source/drain diffusion areas and peripheries are updated when you change the length and width values.  When using design variables only the length or width value is changed by the parameter since they are inserted at simulation time and the simulator doesn't know about the PDK callbacks.

    So to answer your question, the "real" results are those from your second case where you have fixed values in your design.  You can also achieve these identical results if you use parameterization in ADE XL as this flow triggers the callbacks when updating parameter values prior to netlisting.

    Regards,

    TOM

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information