ADE-L simulation problem

Hi,

The most likely cause of the differences in simulation results is that in the case where you are putting the fixed values in the schematics the callbacks associated with those parameter are being executed.  This means that secondary parameters such as source/drain diffusion areas and peripheries are updated when you change the length and width values.  When using design variables only the length or width value is changed by the parameter since they are inserted at simulation time and the simulator doesn't know about the PDK callbacks.

So to answer your question, the "real" results are those from your second case where you have fixed values in your design.  You can also achieve these identical results if you use parameterization in ADE XL as this flow triggers the callbacks when updating parameter values prior to netlisting.

Regards,

TOM

I would in general say that this is indicative of a poorly designed PDK - if using design variables it gives incorrect results, then that is really a fault of the PDK. However, as Tom points out, the callback handling in ADE XL can compensate for this.

Regards,

Andrew.

Dear Goncalo,

> Is there any way to get the "real" results? I mean, the same result for both cases?

Tom and Andrew are both correct - as usual. I have experienced this many times with our PDK and have spoken to our PDK designers.

If you are looking to achieve simulation repeatability on the order of 1% in a schematic based simulation (as from your GBW product differences), my personal recommendation is that you create a physical layout of the specific circuit and simulate its performance using the resulting extracted view. In a schematic based simulation, effects such as the actual parasitics to the gate, gate-drain capacitances due to surrounding features, trace resistances/capacitances, and MOS stress related parameters are only "best guess" estimates. As a result, it is not uncommon to observe differences between schematic and extracted view simulation results that far exceed 1%. Hence, my thought is, to avoid you attempting to "over optimize" your schematic design and use your valuable time doing so, request a physical layout and perform optimization using the resulting extracted view. You may also be interested in Cadence's electrically aware design flow that provides a more real time view of parasitics in real time during physical layout.

Of course, please use your best discretion concerning my thoughts!

Shawn

Thank you all very much!!

Just a quick question out of the scope of this thread, but regarding the OTA circuit.

The calculation of the slew-rate is given by SR=Iout/CL? Or in this two-stage amplifier I must use another formula?

Dear Goncalo,

> The calculation of the slew-rate is given by SR=Iout/CL? Or in this
> two-stage amplifier I must use another formula?

I may not be understanding your question completely - and apologize if I am not! My personal thought is that you need to measure the slew rate of the output waveform in a transient simulation in lieu of relying on the formula to assure an accurate slew rate estimate.

Why is this my thinking?

The "formula" you provide assumes that the output impedance of the feedback amplifier can be modeled as an ideal current source with value Iout. In reality, the amplifier  possesses a finite output series resistance, and the output resistance will be a function of the output voltage (node "out"). For example, as the voltage of "out" approaches your VDD, the folded cascode pmos current source will have a reduced output impedance and reduce the gain of "amplifier2" significantly and, I assume, increase the output series resistance of its model relative to lower "out" voltages (and ehnce change Iout). I do not know at what output voltage level you are most concerned with measuring the slew rate - and hence this change in output current with output voltage might be significant. By measuring the output slew rate in a transient simulation, my thought is that you can better estimate the slew rate over the specific output voltage range you are interested.

I hope I understood your question and my thoughts make sense to you.

Shawn