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ADE-L simulation problem

gonsays1

Hello,

I've been designing a Two-stage CMOS OTA folded cascode amplifier and now I'm simulating the circuit, in order to get the values of certain parameters (slew-rate, small signal gain, bandwidth, phase margin and GBW product).

The first image is the simulation bench, the second image is the schematic of the Amplifier2 symbol and the third image are the properties of the MOS transistors.

First test:

I've started to simulate the circuit on ADE-L using adequated variables for the dimensions of each transistor (as an example: transistor M11 will have width strip and width defined as variable W11 and length as L11).

I've loaded all the variables to the ADE-L and gave them suitable values. On the output, I've used the calculator to get the functions of the referred parameters, getting the following results:

Av=70.85dB
SR=205.3M
Bw=67.47kHz
PM=62.51
GBW=235.9M

 

Second test:

After getting those results, I've replaced the variables on the transistor properties for exactly the same value used as the variable (as an example you can check the last image: for the transistor M5 on the ADE-L I had L5=0.55u and W5=13.5u - on that image you can see that I've changed L5 for 0.55u, for instance).

After replacing all the variables for their associated value on the simulation I got different values for the parameters (using the same dimensions):

Av=70.82dB
SR=201.5M
Bw=67.12k
PM=56.83
GBW=234M

Problem:


As you can see, it makes no sense using the same dimensions (with and without variables on the transistor properties) and getting different results.

Is there any way to get the "real" results? I mean, the same result for both cases?

The last image shows the properties of the transistors (on the 2nd test - with assigned values), is there any option that should be changed?

Thank you very much in advance! :)

Best Regards,

G

Simulation schematic:

Amplifier2 schematic:

 

Transistor properties (schematic):

Parents

  • Dear Goncalo,

    > Is there any way to get the "real" results? I mean, the same result for both cases?

    Tom and Andrew are both correct - as usual. I have experienced this many times with our PDK and have spoken to our PDK designers.

    If you are looking to achieve simulation repeatability on the order of 1% in a schematic based simulation (as from your GBW product differences), my personal recommendation is that you create a physical layout of the specific circuit and simulate its performance using the resulting extracted view. In a schematic based simulation, effects such as the actual parasitics to the gate, gate-drain capacitances due to surrounding features, trace resistances/capacitances, and MOS stress related parameters are only "best guess" estimates. As a result, it is not uncommon to observe differences between schematic and extracted view simulation results that far exceed 1%. Hence, my thought is, to avoid you attempting to "over optimize" your schematic design and use your valuable time doing so, request a physical layout and perform optimization using the resulting extracted view. You may also be interested in Cadence's electrically aware design flow that provides a more real time view of parasitics in real time during physical layout.

    Of course, please use your best discretion concerning my thoughts!

    Shawn

Reply

  • Dear Goncalo,

    > Is there any way to get the "real" results? I mean, the same result for both cases?

    Tom and Andrew are both correct - as usual. I have experienced this many times with our PDK and have spoken to our PDK designers.

    If you are looking to achieve simulation repeatability on the order of 1% in a schematic based simulation (as from your GBW product differences), my personal recommendation is that you create a physical layout of the specific circuit and simulate its performance using the resulting extracted view. In a schematic based simulation, effects such as the actual parasitics to the gate, gate-drain capacitances due to surrounding features, trace resistances/capacitances, and MOS stress related parameters are only "best guess" estimates. As a result, it is not uncommon to observe differences between schematic and extracted view simulation results that far exceed 1%. Hence, my thought is, to avoid you attempting to "over optimize" your schematic design and use your valuable time doing so, request a physical layout and perform optimization using the resulting extracted view. You may also be interested in Cadence's electrically aware design flow that provides a more real time view of parasitics in real time during physical layout.

    Of course, please use your best discretion concerning my thoughts!

    Shawn

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