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ADE-L simulation problem

gonsays1

Hello,

I've been designing a Two-stage CMOS OTA folded cascode amplifier and now I'm simulating the circuit, in order to get the values of certain parameters (slew-rate, small signal gain, bandwidth, phase margin and GBW product).

The first image is the simulation bench, the second image is the schematic of the Amplifier2 symbol and the third image are the properties of the MOS transistors.

First test:

I've started to simulate the circuit on ADE-L using adequated variables for the dimensions of each transistor (as an example: transistor M11 will have width strip and width defined as variable W11 and length as L11).

I've loaded all the variables to the ADE-L and gave them suitable values. On the output, I've used the calculator to get the functions of the referred parameters, getting the following results:

Av=70.85dB
SR=205.3M
Bw=67.47kHz
PM=62.51
GBW=235.9M

 

Second test:

After getting those results, I've replaced the variables on the transistor properties for exactly the same value used as the variable (as an example you can check the last image: for the transistor M5 on the ADE-L I had L5=0.55u and W5=13.5u - on that image you can see that I've changed L5 for 0.55u, for instance).

After replacing all the variables for their associated value on the simulation I got different values for the parameters (using the same dimensions):

Av=70.82dB
SR=201.5M
Bw=67.12k
PM=56.83
GBW=234M

Problem:


As you can see, it makes no sense using the same dimensions (with and without variables on the transistor properties) and getting different results.

Is there any way to get the "real" results? I mean, the same result for both cases?

The last image shows the properties of the transistors (on the 2nd test - with assigned values), is there any option that should be changed?

Thank you very much in advance! :)

Best Regards,

G

Simulation schematic:

Amplifier2 schematic:

 

Transistor properties (schematic):

Parents

  • Dear Goncalo,

    > The calculation of the slew-rate is given by SR=Iout/CL? Or in this
    > two-stage amplifier I must use another formula?

    I may not be understanding your question completely - and apologize if I am not! My personal thought is that you need to measure the slew rate of the output waveform in a transient simulation in lieu of relying on the formula to assure an accurate slew rate estimate.

    Why is this my thinking?


    The "formula" you provide assumes that the output impedance of the feedback amplifier can be modeled as an ideal current source with value Iout. In reality, the amplifier  possesses a finite output series resistance, and the output resistance will be a function of the output voltage (node "out"). For example, as the voltage of "out" approaches your VDD, the folded cascode pmos current source will have a reduced output impedance and reduce the gain of "amplifier2" significantly and, I assume, increase the output series resistance of its model relative to lower "out" voltages (and ehnce change Iout). I do not know at what output voltage level you are most concerned with measuring the slew rate - and hence this change in output current with output voltage might be significant. By measuring the output slew rate in a transient simulation, my thought is that you can better estimate the slew rate over the specific output voltage range you are interested.

    I hope I understood your question and my thoughts make sense to you.

    Shawn

Reply

  • Dear Goncalo,

    > The calculation of the slew-rate is given by SR=Iout/CL? Or in this
    > two-stage amplifier I must use another formula?

    I may not be understanding your question completely - and apologize if I am not! My personal thought is that you need to measure the slew rate of the output waveform in a transient simulation in lieu of relying on the formula to assure an accurate slew rate estimate.

    Why is this my thinking?


    The "formula" you provide assumes that the output impedance of the feedback amplifier can be modeled as an ideal current source with value Iout. In reality, the amplifier  possesses a finite output series resistance, and the output resistance will be a function of the output voltage (node "out"). For example, as the voltage of "out" approaches your VDD, the folded cascode pmos current source will have a reduced output impedance and reduce the gain of "amplifier2" significantly and, I assume, increase the output series resistance of its model relative to lower "out" voltages (and ehnce change Iout). I do not know at what output voltage level you are most concerned with measuring the slew rate - and hence this change in output current with output voltage might be significant. By measuring the output slew rate in a transient simulation, my thought is that you can better estimate the slew rate over the specific output voltage range you are interested.

    I hope I understood your question and my thoughts make sense to you.

    Shawn

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