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  3. Layout XL: "Connectivity->Update->Components and Nets" resets...

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Layout XL: "Connectivity->Update->Components and Nets" resets all my pins

PNadeau
PNadeau over 10 years ago

Dear folks,

Sometimes I make a few schematic changes and then in Layout XL I use Connectivity->Update->Components And Nets to update the Layout connectivity.  I select "Update nets and Instance name mismatches only" and "Update Net Signal Type" and click OK.

When I do this, the tool moves all of the pins I have already placed to the lower left-hand corner of the layout, despite nothing really changing on most of these nets, causing me to have to place them all again.

Is there a way to prevent this behaviour?  Ideally I'd like to leave most of the pins alone if nothing has changed on those nets.

If it's relevant, the pins were initially placed using Connectivity->Generate->Selected From Source, and using the "Unplaced" and "Place Individually" mode.  The pin and label are placed on the "pin" LPP for the relevant metal.

IC6.1.6.101, RHEL 6

Thanks in advance.

Cheers,
Phil

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  • ColinSutlieff
    ColinSutlieff over 10 years ago

    Hi Phil,

    in the pop-up form, select the tab "IO pins" and unclick the "create" check box (at the top in the "specify default values for all pins" section)

    Regards

     

    Colin

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  • PNadeau
    PNadeau over 10 years ago

    Hi Colin,

    Thanks.  I tried your suggestion but it didn't quite work.  For me, when I click the "Update Nets and Instance Mismatches Only," most options, including the I/O Pins tab, are greyed out (attached screenshot). I can make the I/O Pins tab active by unselecting "Update Nets..." and Selecting "I/O Pins" in the "Generate" section.  Then I tried:

    1) Unchecking "Create" in the "Specify Default Values", going back and checking the "Update Nets..." (which greys out everything) and running,

    2) Unchecking "Create" and not selecting "Update nets..." (leaves all options still active) and running

    3) Unchecking "Create", going back to "Update" tab and unselecting all options except for "I/O Pins" (to leave the I/O Pins tab active) and running

    All three of these still moved 100 of my pins to the lower left of the layout. I also tried adding the "Locked" constraint to the pins using the constraint manager, but they are still moved by "Update nets..." (and cannot be moved further unless I unlock them).

    Is there another way to update the connectivity without having to re-place all the pins?

    Cheers,

    Phil

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  • PNadeau
    PNadeau over 10 years ago
    Actually, I just tested with no check-boxes enabled at all in the "Update" tab and it still moves the pins....
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  • ColinSutlieff
    ColinSutlieff over 10 years ago

    Hi Phil,

    What I explained should work.

    I am trying to think why it is not working in your case.

    Perhaps you could check to see if there is a fundamental problem that is causing the tool to re-generate your pins.

    Run connectivity->check->against source on the layout with the pins already placed.

    Do you see any errors regarding pins/nets?

    When running GFS/UCN the tool also looks at a view called "physconfig" to perform mapping.

    This view defines logical to physical mapping.

    To edit this view, click Launch->configure physical hierarchy

    Click soft block (cyclic field at the top) and select soft block

    In the middle pane click your top-level cell.

    You should see all your IO pins listed, together with other parameters like layer, width etc. If these values differ from your pins in the layout this may be the reason for the regenerated pins. If you make any changes here, don't forget to save.

    Otherwise I am running out of ideas. You may need to contact customer support to investigate further.

     

    Hope this helps

    Colin

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  • PNadeau
    PNadeau over 10 years ago

    Hi Colin,

    Thanks very much for your persistence.  I can report the following:

    I tried check against source, and there was only one warning about a pin direction being mismatched. I fixed this and now there are no messages in CAS, but UCN still moves all the pins.

    I looked at the physical hierarchy, soft block settings.  If I click my top cell in the middle pane (the very top line with the folder beside it), the I/O pins are not listed in the I/O tab (it is completely blank), but if I go to the "Custom" subfolder I can see all my sub-cells, and selecting one of those shows the pins for that sub-cell in the I/O tab (but the top cell does not appear in the list).   It is possible this is expected behaviour, or at least unrelated to by UCN problems since I just tried this on a small cell of mine (only 4 pins) that actually does not suffer from the UCN problem (the pins are left in place somehow), and it too does not have pins listed for the top cell in a similar way.

    I am out of ideas too. Thanks for your help!

    Phil

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  • ColinSutlieff
    ColinSutlieff over 10 years ago

    Hi Phil,

    One last suggestion:

    Check if the pins have a property called "lxPlacementStatus"

    If yes, delete the property

    This may fix the problem.

    It seems that this property gets generated when you use the generate->selected from source ( with option "place individually" set)

    This happened in earlier releases.

    Let us know if this fixes the problem

     

    Colin

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  • PNadeau
    PNadeau over 10 years ago

    Hi Colin,

    You've hit it, this was the solution. All my pins had the lxPlacementStatus property.  After deleting it then update components and nets works properly and the pins stay in place.

    This is great, thanks for your help,

    Phil

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