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Layout XL: "Connectivity->Update->Components and Nets" resets all my pins

PNadeau

Dear folks,

Sometimes I make a few schematic changes and then in Layout XL I use Connectivity->Update->Components And Nets to update the Layout connectivity.  I select "Update nets and Instance name mismatches only" and "Update Net Signal Type" and click OK.

When I do this, the tool moves all of the pins I have already placed to the lower left-hand corner of the layout, despite nothing really changing on most of these nets, causing me to have to place them all again.

Is there a way to prevent this behaviour?  Ideally I'd like to leave most of the pins alone if nothing has changed on those nets.

If it's relevant, the pins were initially placed using Connectivity->Generate->Selected From Source, and using the "Unplaced" and "Place Individually" mode.  The pin and label are placed on the "pin" LPP for the relevant metal.

IC6.1.6.101, RHEL 6

Thanks in advance.

Cheers,
Phil

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  • ColinSutlieff

    Hi Phil,

    What I explained should work.

    I am trying to think why it is not working in your case.

    Perhaps you could check to see if there is a fundamental problem that is causing the tool to re-generate your pins.

    Run connectivity->check->against source on the layout with the pins already placed.

    Do you see any errors regarding pins/nets?

    When running GFS/UCN the tool also looks at a view called "physconfig" to perform mapping.

    This view defines logical to physical mapping.

    To edit this view, click Launch->configure physical hierarchy

    Click soft block (cyclic field at the top) and select soft block

    In the middle pane click your top-level cell.

    You should see all your IO pins listed, together with other parameters like layer, width etc. If these values differ from your pins in the layout this may be the reason for the regenerated pins. If you make any changes here, don't forget to save.

    Otherwise I am running out of ideas. You may need to contact customer support to investigate further.

     

    Hope this helps

    Colin

Reply
  • ColinSutlieff

    Hi Phil,

    What I explained should work.

    I am trying to think why it is not working in your case.

    Perhaps you could check to see if there is a fundamental problem that is causing the tool to re-generate your pins.

    Run connectivity->check->against source on the layout with the pins already placed.

    Do you see any errors regarding pins/nets?

    When running GFS/UCN the tool also looks at a view called "physconfig" to perform mapping.

    This view defines logical to physical mapping.

    To edit this view, click Launch->configure physical hierarchy

    Click soft block (cyclic field at the top) and select soft block

    In the middle pane click your top-level cell.

    You should see all your IO pins listed, together with other parameters like layer, width etc. If these values differ from your pins in the layout this may be the reason for the regenerated pins. If you make any changes here, don't forget to save.

    Otherwise I am running out of ideas. You may need to contact customer support to investigate further.

     

    Hope this helps

    Colin

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