Stats

  • Locked Locked
  • Replies 3
  • Subscribers 125
  • Views 13782
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Usage of (* cds_inherited_parameter *)

chenchen

Hi all,

I try the simple case in Verilog-A document and I want to obtain "different" values of mismatch parameter in single Verilog-A module.

// I want to use "single" random variable for different parameters w/ mismatch

// variation.scs

section my_variation

parameters monteres=0

statistics {

  mismatch {
    vary monteres dist=gauss std=5
  }
}

endsection my_variation

//////////////////////////////////////////////////////////

// pseudo code 

include "variation.scs"  my_variation

(* cds_inherited_parameter *) parameter real monteres = 0;
parameter real r = 1k;

localparam real r1_effective = r + monteres; 

localparam real r2_effective = r + monteres; 

V(vp1, vn1) <+ (r1_effective)*I(vp1, vn1);

V(vp2, vn2) <+ (r2_effective)*I(vp2, vn2);

//////////////////////////////////////////////////////////

I expect two different random values of r1_effective and r2_effective, but I just got one random value during each Monte Carlo iteration ( r1_effective=r2_effective)

Anyone knows what is correct usage for such cases? (I want r1_effective != r2_effective)

Many thanks.

  • Why would you expect to have two different values? You'll have one value of monteres per instance of the Verilog-A module, so the value of both r1_effective and r2_effective will be the same of course. You will need to have two statistical parameters in the statistics block and cds_inherited_parameter for them both in the Verilog-A.

    Regards,

    Andrew.

  • My usage is that there may be several thousand of random values in single Verilog-A module and all random variables are independent during Monte Carlo simulation. I try to use one variable in "variation.scs" not several thousand of variables because I think that would induce performance issues in Verilog-A compiling and execution(simulation). Is there any solution to do that ? One solution is that I still use one variable in "variation.scs" and use several thousand of instances in single Verilog-A module. However, it seems to face similar performance issue because it just change the numerous description from "variation.scs" to "main code". Thanks.

  • Having lots of instances of the Verilog-A is almost certainly less efficient than having a single instance with many parameters. The only problem with having a huge number of mismatch parameters is that these need to be generated for every instance in the design (not just the instances that use them), so that's also expensive. However, given the fact that the random numbers are generated for each mismatch parameter and for each instance, there's no getting around this fact...

    Maybe you should contact customer support so that we can talk in more detail about your unusual requirements.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.