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layout of MIMCAPS_MM capacitor in virtuoso 6.1.5

pratibhads2805

hello sir,

I want to know about the mimcaps_mm capacitor layout. what are  the upper and lower layers and how to connect them?

I'am attaching a snapshot of layout.

thank you sir in advance.

  • It would be rather helpful to know which technology (which PDK) you're using. "mimcaps_mm" is a name specific to a particular PDK - nobody will be able to answer this unless they know which technology you're talking about (unless they happen to recognise the component name by luck).

    Regards,

    Andrew.

  • MIMcaps have to metal layers with "dielectric" (incase of PDK the insulator between to consecutive metal layers).One is usually supposed to connect the bottom and top metal cells.Some PDKs automatically route connections when extracted.As far as I know , you have to manually route MIMcap cells in gpdk045.As Andrew said, it's wise to check PDK model report for layer definition.

  • I've taken MIMCAPS_MM from UMC_18_CMOS, i forgot to mention it, sorry for that. I also want to know about the third terminal of RNNPO_MM from UMC_18_CMOS. I guess the third terminal is gnd, but when I'am connecting gnd to third terminal via metal1 it is showing welnotr_StampErrorFloat.

    Thank you sir for your reply.

  • Stamperror float : Sounds like substrate not grounded.You would be surprised to see performance change with B terminal connected to ground and kept floating.If you look at device model file, grounding the third terminal will most likely pave a way to include Cox and Csub to your MIMcap model.
  • in reply to Andrew Beckett

    can we create our own  mim capacitor layout if yes then how please explain. 

    thanks and regads 

    kshitij

  • in reply to kshitij
    kshitij said:
    can we create our own  mim capacitor layout if yes then how please explain.

    It rather depends on whether the process you're using has the special dielectric layer needed to form a mimcap. If it does, then the PDK is rather likely to have a device to produce the layout for a MIM capacitor. This special layer is usually thinner to allow a higher capacitance than a normal metal to metal capacitor.

    Regards,

    Andrew.

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